Wang Qing Pei | 0ede4c0 | 2010-08-17 15:19:32 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com> |
| 5 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <boot/tables.h> |
| 26 | #include <cpu/x86/msr.h> |
| 27 | #include <cpu/amd/mtrr.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <southbridge/amd/sb700/sb700.h> |
| 30 | #include "chip.h" |
| 31 | |
| 32 | #define SMBUS_IO_BASE 0x6000 |
| 33 | |
| 34 | uint64_t uma_memory_base, uma_memory_size; |
| 35 | |
| 36 | void set_pcie_dereset(void); |
| 37 | void set_pcie_reset(void); |
| 38 | |
| 39 | /* |
| 40 | * the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to |
| 41 | * pull it up before training the slot. |
| 42 | ***/ |
| 43 | void set_pcie_dereset() |
| 44 | { |
| 45 | u16 word; |
| 46 | device_t sm_dev; |
| 47 | /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ |
| 48 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 49 | |
| 50 | word = pci_read_config16(sm_dev, 0xA8); |
| 51 | word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ |
| 52 | word &= ~((1 << 8) | (1 << 10)); |
| 53 | pci_write_config16(sm_dev, 0xA8, word); |
| 54 | } |
| 55 | |
| 56 | void set_pcie_reset() |
| 57 | { |
| 58 | u16 word; |
| 59 | device_t sm_dev; |
| 60 | /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ |
| 61 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 62 | |
| 63 | word = pci_read_config16(sm_dev, 0xA8); |
| 64 | word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ |
| 65 | word &= ~((1 << 8) | (1 << 10)); |
| 66 | pci_write_config16(sm_dev, 0xA8, word); |
| 67 | } |
| 68 | |
| 69 | #if 0 /* not tested yet. */ |
| 70 | /******************************************************** |
| 71 | * board uses SB700 GPIO9 to detect IDE_DMA66. |
| 72 | * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to |
| 73 | * get the cable type, 40 pin or 80 pin? |
| 74 | ********************************************************/ |
| 75 | static void get_ide_dma66(void) |
| 76 | { |
| 77 | u8 byte; |
| 78 | /*u32 sm_dev, ide_dev; */ |
| 79 | device_t sm_dev, ide_dev; |
| 80 | |
| 81 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 82 | |
| 83 | byte = pci_read_config8(sm_dev, 0xA9); |
| 84 | byte |= (1 << 5); /* Set Gpio9 as input */ |
| 85 | pci_write_config8(sm_dev, 0xA9, byte); |
| 86 | |
| 87 | ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); |
| 88 | byte = pci_read_config8(ide_dev, 0x56); |
| 89 | byte &= ~(7 << 0); |
| 90 | if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) |
| 91 | byte |= 2 << 0; /* mode 2 */ |
| 92 | else |
| 93 | byte |= 5 << 0; /* mode 5 */ |
| 94 | pci_write_config8(ide_dev, 0x56, byte); |
| 95 | } |
| 96 | #endif /* get_ide_dma66() */ |
| 97 | |
| 98 | /************************************************* |
| 99 | * enable the dedicated function in this board. |
| 100 | * This function called early than rs780_enable. |
| 101 | *************************************************/ |
| 102 | static void pa78vm5_enable(device_t dev) |
| 103 | { |
| 104 | /* Leave it for furture use. */ |
| 105 | /* struct mainboard_config *mainboard = |
| 106 | (struct mainboard_config *)dev->chip_info; */ |
| 107 | |
| 108 | printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); |
| 109 | |
| 110 | #if (CONFIG_GFXUMA == 1) |
| 111 | msr_t msr, msr2; |
| 112 | |
| 113 | /* TOP_MEM: the top of DRAM below 4G */ |
| 114 | msr = rdmsr(TOP_MEM); |
| 115 | printk |
| 116 | (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 117 | __func__, msr.lo, msr.hi); |
| 118 | |
| 119 | /* TOP_MEM2: the top of DRAM above 4G */ |
| 120 | msr2 = rdmsr(TOP_MEM2); |
| 121 | printk |
| 122 | (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", |
| 123 | __func__, msr2.lo, msr2.hi); |
| 124 | |
| 125 | /* refer to UMA Size Consideration in 780 BDG. */ |
| 126 | switch (msr.lo) { |
| 127 | case 0x10000000: /* 256M system memory */ |
| 128 | uma_memory_size = 0x4000000; /* 64M recommended UMA */ |
| 129 | break; |
| 130 | |
| 131 | case 0x20000000: /* 512M system memory */ |
| 132 | uma_memory_size = 0x8000000; /* 128M recommended UMA */ |
| 133 | break; |
| 134 | |
| 135 | default: /* 1GB and above system memory */ |
| 136 | uma_memory_size = 0x10000000; /* 256M recommended UMA */ |
| 137 | break; |
| 138 | } |
| 139 | |
| 140 | uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ |
| 141 | printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", |
| 142 | __func__, uma_memory_size, uma_memory_base); |
| 143 | |
| 144 | /* TODO: TOP_MEM2 */ |
| 145 | #else |
| 146 | uma_memory_size = 0x8000000; /* 128M recommended UMA */ |
| 147 | uma_memory_base = 0x38000000; /* 1GB system memory supposed */ |
| 148 | #endif |
| 149 | |
| 150 | set_pcie_dereset(); |
| 151 | /* get_ide_dma66(); */ |
| 152 | } |
| 153 | |
| 154 | int add_mainboard_resources(struct lb_memory *mem) |
| 155 | { |
| 156 | /* UMA is removed from system memory in the northbridge code, but |
| 157 | * in some circumstances we want the memory mentioned as reserved. |
| 158 | */ |
| 159 | #if (CONFIG_GFXUMA == 1) |
| 160 | printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", |
| 161 | uma_memory_base, uma_memory_size); |
| 162 | lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, |
| 163 | uma_memory_size); |
| 164 | #endif |
| 165 | return 0; |
| 166 | } |
| 167 | |
| 168 | struct chip_operations mainboard_ops = { |
| 169 | CHIP_NAME("AMD PA78VM5 Mainboard") |
| 170 | .enable_dev = pa78vm5_enable, |
| 171 | }; |