| York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 1 | config BROADWELL_DE_FSP_SPECIFIC_OPTIONS |
| 2 | def_bool y |
| 3 | select PLATFORM_USES_FSP1_0 |
| 4 | select USE_GENERIC_FSP_CAR_INC |
| 5 | select FSP_USES_UPD |
| 6 | |
| 7 | config FSP_FILE |
| 8 | string |
| Patrick Rudolph | e77d6dc | 2019-01-08 11:37:18 +0100 | [diff] [blame] | 9 | default "3rdparty/fsp/BroadwellDEFspBinPkg/FspBin/BROADWELLDE_FSP.bin" |
| York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 10 | help |
| 11 | The path and filename of the Intel FSP binary for this platform. |
| 12 | |
| Patrick Rudolph | e77d6dc | 2019-01-08 11:37:18 +0100 | [diff] [blame] | 13 | config FSP_HEADER_PATH |
| 14 | string |
| 15 | default "$(top)/3rdparty/fsp/BroadwellDEFspBinPkg/include/" |
| 16 | |
| 17 | config FSP_SRC_PATH |
| 18 | string |
| 19 | default "$(top)/3rdparty/fsp/BroadwellDEFspBinPkg/include/fspsupport.c" |
| 20 | |
| York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 21 | config FSP_LOC |
| 22 | hex |
| 23 | default 0xffeb0000 |
| 24 | help |
| 25 | The location in CBFS that the FSP is located. This must match the |
| 26 | value that is set in the FSP binary. If the FSP needs to be moved, |
| 27 | rebase the FSP with Intel's BCT (tool). |
| 28 | |
| 29 | The Broadwell-DE FSP is built with a preferred base address of |
| 30 | 0xffeb0000. |
| 31 | |
| Werner Zeh | cacc5a3 | 2018-04-05 07:41:52 +0200 | [diff] [blame] | 32 | config DCACHE_RAM_BASE |
| 33 | hex |
| 34 | default 0xfe100000 |
| 35 | help |
| 36 | This address needs to match the setup performed inside FSP. |
| 37 | On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000. |
| 38 | |
| 39 | config DCACHE_RAM_SIZE |
| 40 | hex |
| 41 | default 0x8000 |
| 42 | help |
| 43 | The DCACHE is shared between FSP itself and the rest of the coreboot |
| 44 | stages. A size of 0x8000 works fine while providing enough space for |
| 45 | features like VBOOT in verstage. Further increase to a power of two |
| 46 | aligned value leads to errors in FSP. |
| 47 | |
| York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 48 | config FSP_MEMORY_DOWN |
| 49 | bool "Enable Memory Down" |
| 50 | default n |
| 51 | help |
| 52 | Load SPD data from ROM instead of trying to read from SMBus. |
| 53 | |
| 54 | If the platform has DIMM sockets, say N. If memory is down, say Y and |
| 55 | supply the appropriate SPD data for each Channel/DIMM. |
| 56 | |
| 57 | config FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT |
| 58 | bool "Channel 0, DIMM 0 Present" |
| 59 | default n |
| 60 | depends on FSP_MEMORY_DOWN |
| 61 | help |
| 62 | Select Y if Channel 0, DIMM 0 is present. |
| 63 | |
| 64 | config FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE |
| 65 | string "Channel 0, DIMM 0 SPD File" |
| 66 | default "spd_ch0_dimm0.bin" |
| 67 | depends on FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT |
| 68 | help |
| 69 | Path to the file which contains the SPD data for Channel 0, DIMM 0. |
| 70 | |
| 71 | config FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT |
| 72 | bool "Channel 0, DIMM 1 Present" |
| 73 | default n |
| 74 | depends on FSP_MEMORY_DOWN |
| 75 | help |
| 76 | Select Y if Channel 0, DIMM 1 is present. |
| 77 | |
| 78 | config FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE |
| 79 | string "Channel 0, DIMM 1 SPD File" |
| 80 | default "spd_ch0_dimm1.bin" |
| 81 | depends on FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT |
| 82 | help |
| 83 | Path to the file which contains the SPD data for Channel 0, DIMM 1. |
| 84 | |
| 85 | config FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT |
| 86 | bool "Channel 1, DIMM 0 Present" |
| 87 | default n |
| 88 | depends on FSP_MEMORY_DOWN |
| 89 | help |
| 90 | Select Y if Channel 1, DIMM 0 is present. |
| 91 | |
| 92 | config FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE |
| 93 | string "Channel 1, DIMM 0 SPD File" |
| 94 | default "spd_ch1_dimm0.bin" |
| 95 | depends on FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT |
| 96 | help |
| 97 | Path to the file which contains the SPD data for Channel 1, DIMM 0. |
| 98 | |
| 99 | config FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT |
| 100 | bool "Channel 1, DIMM 1 Present" |
| 101 | default n |
| 102 | depends on FSP_MEMORY_DOWN |
| 103 | help |
| 104 | Select Y if Channel 1, DIMM 1 is present. |
| 105 | |
| 106 | config FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE |
| 107 | string "Channel 1, DIMM 1 SPD File" |
| 108 | default "spd_ch1_dimm1.bin" |
| 109 | depends on FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT |
| 110 | help |
| 111 | Path to the file which contains the SPD data for Channel 1, DIMM 1. |
| 112 | |
| 113 | config FSP_HYPERTHREADING |
| 114 | bool "Enable Hyper-Threading" |
| 115 | default y |
| 116 | help |
| 117 | Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC. |
| David Hendricks | 99d3ef85 | 2018-04-25 16:47:45 -0700 | [diff] [blame] | 118 | |
| 119 | config FSP_EHCI1_ENABLE |
| 120 | bool "EHCI1 Enable" |
| 121 | default n |
| 122 | help |
| 123 | Enable EHCI controller 1 |
| 124 | |
| 125 | config FSP_EHCI2_ENABLE |
| 126 | bool "EHCI2 Enable" |
| 127 | default n |
| 128 | help |
| 129 | Enable EHCI controller 2 |
| Nico Huber | 0d25e5a | 2019-02-09 13:13:45 +0100 | [diff] [blame^] | 130 | |
| 131 | config FSP_DEBUG_LEVEL |
| 132 | int "FSP debug level (0-3)" |
| 133 | default 0 |
| 134 | range 0 3 |
| 135 | help |
| 136 | Select the debug level, where: |
| 137 | 0: DISABLED |
| 138 | 1: MINIMUM |
| 139 | 2: NORMAL |
| 140 | 3: MAXIMUM |