Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 2 | |
| 3 | #include <types.h> |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 4 | #include <console/console.h> |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Arthur Heymans | 6af3e6f | 2018-04-10 13:18:19 +0200 | [diff] [blame] | 6 | #include <southbridge/intel/common/pmutil.h> |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 7 | #include "i82801jx.h" |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 8 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 9 | /* While we read PMBASE dynamically in case it changed, let's |
| 10 | * initialize it with a sane value |
| 11 | */ |
| 12 | u16 pmbase = DEFAULT_PMBASE; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 13 | |
Arthur Heymans | 6af3e6f | 2018-04-10 13:18:19 +0200 | [diff] [blame] | 14 | void southbridge_smi_monitor(void) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 15 | { |
| 16 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 17 | u32 trap_sts, trap_cycle; |
| 18 | u32 data, mask = 0; |
| 19 | int i; |
| 20 | |
| 21 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 22 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 23 | |
| 24 | trap_cycle = RCBA32(0x1e10); |
| 25 | for (i=16; i<20; i++) { |
| 26 | if (trap_cycle & (1 << i)) |
| 27 | mask |= (0xff << ((i - 16) << 3)); |
| 28 | } |
| 29 | |
Angel Pons | 00f11c0 | 2021-01-10 15:39:12 +0100 | [diff] [blame] | 30 | /* IOTRAP(3) SMI function call (unused) */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 31 | if (IOTRAP(3)) { |
Angel Pons | 00f11c0 | 2021-01-10 15:39:12 +0100 | [diff] [blame] | 32 | printk(BIOS_DEBUG, "SMI function call not implemented\n"); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 33 | return; |
| 34 | } |
| 35 | |
| 36 | /* IOTRAP(2) currently unused |
| 37 | * IOTRAP(1) currently unused */ |
| 38 | |
| 39 | /* IOTRAP(0) SMIC */ |
| 40 | if (IOTRAP(0)) { |
| 41 | if (!(trap_cycle & (1 << 24))) { // It's a write |
| 42 | printk(BIOS_DEBUG, "SMI1 command\n"); |
| 43 | data = RCBA32(0x1e18); |
| 44 | data &= mask; |
| 45 | // if (smi1) |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 46 | // southbridge_smi_command(data); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 47 | // return; |
| 48 | } |
| 49 | // Fall through to debug |
| 50 | } |
| 51 | |
| 52 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); |
| 53 | for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); |
| 54 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 55 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
| 56 | printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); |
| 57 | |
| 58 | if (!(trap_cycle & (1 << 24))) { |
| 59 | /* Write Cycle */ |
| 60 | data = RCBA32(0x1e18); |
| 61 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); |
| 62 | } |
| 63 | #undef IOTRAP |
| 64 | } |
| 65 | |
Arthur Heymans | 6af3e6f | 2018-04-10 13:18:19 +0200 | [diff] [blame] | 66 | void southbridge_finalize_all(void) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 67 | { |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 68 | } |