Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | c484da1 | 2019-11-09 14:29:04 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 3 | #include <console/console.h> |
Arthur Heymans | c484da1 | 2019-11-09 14:29:04 +0100 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 5 | #include <device/smbus_host.h> |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 6 | #include <southbridge/intel/common/gpio.h> |
| 7 | #include <southbridge/intel/common/pmbase.h> |
Angel Pons | 490473e | 2020-06-21 17:10:28 +0200 | [diff] [blame] | 8 | #include <southbridge/intel/common/pmutil.h> |
Arthur Heymans | c484da1 | 2019-11-09 14:29:04 +0100 | [diff] [blame] | 9 | #include "i82801jx.h" |
| 10 | #include "chip.h" |
| 11 | |
| 12 | void i82801jx_lpc_setup(void) |
| 13 | { |
| 14 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
| 15 | const struct device *dev = pcidev_on_root(0x1f, 0); |
| 16 | const struct southbridge_intel_i82801jx_config *config; |
| 17 | |
| 18 | /* Configure serial IRQs.*/ |
| 19 | pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); |
| 20 | /* |
| 21 | * Enable some common LPC IO ranges: |
| 22 | * - 0x2e/0x2f, 0x4e/0x4f often SuperIO |
| 23 | * - 0x60/0x64, 0x62/0x66 often KBC/EC |
| 24 | * - 0x3f0-0x3f5/0x3f7 FDD |
| 25 | * - 0x378-0x37f and 0x778-0x77f LPT |
| 26 | * - 0x2f8-0x2ff COMB |
| 27 | * - 0x3f8-0x3ff COMA |
| 28 | * - 0x208-0x20f GAMEH |
| 29 | * - 0x200-0x207 GAMEL |
| 30 | */ |
| 31 | pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); |
| 32 | pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN |
| 33 | | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN |
| 34 | | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN |
| 35 | | COMB_LPC_EN | COMA_LPC_EN); |
| 36 | |
Arthur Heymans | c484da1 | 2019-11-09 14:29:04 +0100 | [diff] [blame] | 37 | /* Set up generic decode ranges */ |
| 38 | if (!dev || !dev->chip_info) |
| 39 | return; |
| 40 | config = dev->chip_info; |
| 41 | |
| 42 | pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); |
| 43 | pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); |
| 44 | pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); |
| 45 | pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); |
| 46 | } |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 47 | |
Arthur Heymans | 7843bd5 | 2019-11-11 21:56:37 +0100 | [diff] [blame] | 48 | void i82801jx_setup_bars(void) |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 49 | { |
| 50 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
| 51 | |
| 52 | /* Set up RCBA. */ |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 53 | pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 54 | |
| 55 | /* Set up PMBASE. */ |
| 56 | pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); |
| 57 | /* Enable PMBASE. */ |
| 58 | pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); |
| 59 | |
| 60 | /* Set up GPIOBASE. */ |
| 61 | pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 62 | /* Enable GPIO. */ |
| 63 | pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | #define TCO_BASE 0x60 |
| 67 | |
| 68 | void i82801jx_early_init(void) |
| 69 | { |
| 70 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
| 71 | |
Kyösti Mälkki | 11cac78 | 2022-04-07 07:16:48 +0300 | [diff] [blame] | 72 | if (ENV_RAMINIT) |
Kyösti Mälkki | 1cfafe2 | 2020-01-07 12:00:31 +0200 | [diff] [blame] | 73 | enable_smbus(); |
| 74 | |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 75 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
| 76 | i82801jx_setup_bars(); |
| 77 | printk(BIOS_DEBUG, " done.\n"); |
| 78 | |
| 79 | setup_pch_gpios(&mainboard_gpio_map); |
| 80 | |
| 81 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 82 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
| 83 | write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ |
| 84 | write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ |
| 85 | write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ |
| 86 | printk(BIOS_DEBUG, " done.\n"); |
| 87 | |
| 88 | /* Enable IOAPIC */ |
| 89 | RCBA8(OIC) = 0x3; |
| 90 | RCBA8(OIC); |
| 91 | |
| 92 | /* Initialize power management initialization |
| 93 | register early as it affects reboot behavior. */ |
| 94 | /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 |
| 95 | and 0xe (required if ME is disabled but present), bit 31 locks it. |
| 96 | The other bits are 'must write'. */ |
| 97 | u8 reg8 = pci_read_config8(d31f0, 0xac); |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 98 | |
| 99 | /* FIXME: It's a 8-bit variable!!! */ |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 100 | reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); |
| 101 | pci_write_config8(d31f0, 0xac, reg8); |
| 102 | |
| 103 | /* TODO: If RTC power failed, reset RTC state machine |
| 104 | (set, then reset RTC 0x0b bit7) */ |
| 105 | |
| 106 | /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) |
| 107 | before they get cleared. */ |
| 108 | } |