Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 2 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 3 | #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H |
| 4 | #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 5 | |
Felix Singer | f4842bb | 2024-01-12 21:21:06 +0100 | [diff] [blame] | 6 | #include <stdbool.h> |
Elyes HAOUAS | c4e4193 | 2018-11-01 11:29:50 +0100 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 9 | enum { |
| 10 | THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, |
| 11 | THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 |
| 12 | }; |
| 13 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 14 | struct southbridge_intel_i82801jx_config { |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 15 | /** |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 16 | * GPI Routing configuration |
| 17 | * |
| 18 | * Only the lower two bits have a meaning: |
| 19 | * 00: No effect |
| 20 | * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 21 | * 10: SCI (if corresponding GPIO_EN bit is also set) |
| 22 | * 11: reserved |
| 23 | */ |
| 24 | uint8_t gpi0_routing; |
| 25 | uint8_t gpi1_routing; |
| 26 | uint8_t gpi2_routing; |
| 27 | uint8_t gpi3_routing; |
| 28 | uint8_t gpi4_routing; |
| 29 | uint8_t gpi5_routing; |
| 30 | uint8_t gpi6_routing; |
| 31 | uint8_t gpi7_routing; |
| 32 | uint8_t gpi8_routing; |
| 33 | uint8_t gpi9_routing; |
| 34 | uint8_t gpi10_routing; |
| 35 | uint8_t gpi11_routing; |
| 36 | uint8_t gpi12_routing; |
| 37 | uint8_t gpi13_routing; |
| 38 | uint8_t gpi14_routing; |
| 39 | uint8_t gpi15_routing; |
| 40 | |
| 41 | uint32_t gpe0_en; |
| 42 | uint16_t alt_gp_smi_en; |
| 43 | |
| 44 | /* IDE configuration */ |
| 45 | uint8_t sata_port_map : 6; |
Elyes Haouas | a7f55af | 2023-09-09 10:18:03 +0200 | [diff] [blame] | 46 | bool sata_clock_request; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 47 | |
Elyes Haouas | a7f55af | 2023-09-09 10:18:03 +0200 | [diff] [blame] | 48 | bool c4onc3_enable; |
| 49 | bool c5_enable; |
| 50 | bool c6_enable; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 51 | |
Arthur Heymans | 7e397ac | 2022-02-18 14:21:45 +0100 | [diff] [blame] | 52 | unsigned int throttle_duty : 3; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 53 | |
| 54 | /* Bit mask to tell whether a PCIe slot is implemented as slot. */ |
Arthur Heymans | 7e397ac | 2022-02-18 14:21:45 +0100 | [diff] [blame] | 55 | unsigned int pcie_slot_implemented : 6; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 56 | |
| 57 | /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ |
| 58 | struct { |
| 59 | uint8_t value : 8; |
| 60 | uint8_t scale : 2; |
| 61 | } pcie_power_limits[6]; |
| 62 | |
Felix Singer | f4842bb | 2024-01-12 21:21:06 +0100 | [diff] [blame] | 63 | bool pcie_hotplug_map[8]; |
Arthur Heymans | c484da1 | 2019-11-09 14:29:04 +0100 | [diff] [blame] | 64 | |
| 65 | /* Additional LPC IO decode ranges */ |
| 66 | uint32_t gen1_dec; |
| 67 | uint32_t gen2_dec; |
| 68 | uint32_t gen3_dec; |
| 69 | uint32_t gen4_dec; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 70 | }; |
| 71 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 72 | #endif /* SOUTHBRIDGE_INTEL_I82801JX_CHIP_H */ |