| Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 2 | |
| 3 | #include <device/pci_def.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include "i82801gx.h" |
| 6 | |
| 7 | /* Chipset Initialization Registers magic */ |
| 8 | void ich7_setup_cir(void) |
| 9 | { |
| 10 | uint32_t reg32; |
| 11 | uint8_t revision = pci_read_config8(PCI_DEV(0, 31, 0), PCI_REVISION_ID); |
| 12 | uint16_t pci_id = pci_read_config16(PCI_DEV(0, 31, 0), PCI_DEVICE_ID); |
| 13 | |
| 14 | RCBA32(0x0088) = 0x0011d000; |
| 15 | RCBA16(0x01fc) = 0x060f; |
| 16 | RCBA32(0x01f4) = 0x86000040; |
| 17 | /* Although bit 6 is set, it is not read back */ |
| 18 | RCBA32(0x0214) = 0x10030549; |
| 19 | RCBA32(0x0218) = 0x00020504; |
| 20 | RCBA8(0x0220) = 0xc5; |
| Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 21 | RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0); |
| 22 | RCBA16(0x0200) = 0x2008; |
| 23 | RCBA8(0x2027) = 0x0d; |
| 24 | RCBA16(0x3e08) |= (1 << 7); |
| 25 | RCBA16(0x3e48) |= (1 << 7); |
| 26 | RCBA32(0x3e0e) |= (1 << 7); |
| 27 | RCBA32(0x3e4e) |= (1 << 7); |
| 28 | |
| 29 | /* Only on mobile variants of revision b0 or later */ |
| 30 | switch (pci_id) { |
| 31 | case 0x27b9: |
| 32 | case 0x27bc: |
| 33 | case 0x27bd: |
| 34 | if (revision >= 2) { |
| 35 | reg32 = RCBA32(0x2034); |
| 36 | reg32 &= ~(0x0f << 16); |
| 37 | reg32 |= (5 << 16); |
| 38 | RCBA32(0x2034) = reg32; |
| 39 | } |
| Arthur Heymans | 39bde7c | 2019-10-21 20:02:14 +0200 | [diff] [blame] | 40 | /* FERR# MUX Enable (FME) */ |
| 41 | reg32 = RCBA32(GCS); |
| 42 | reg32 |= (1 << 6); |
| 43 | RCBA32(GCS) = reg32; |
| Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 44 | } |
| 45 | } |