Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 2 | |
| 3 | #include <assert.h> |
Marc Jones | 63e2a84 | 2020-12-02 11:33:02 -0700 | [diff] [blame] | 4 | #include <intelblocks/acpi.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 5 | #include <soc/pci_devs.h> |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 6 | #include <soc/util.h> |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 7 | #include <stdint.h> |
Marc Jones | 9f55574 | 2020-09-24 16:35:56 -0600 | [diff] [blame] | 8 | |
Marc Jones | 31ed885 | 2021-01-15 13:29:14 -0700 | [diff] [blame] | 9 | #include "chip.h" |
| 10 | |
| 11 | /* |
| 12 | * List of supported C-states in this processor. |
| 13 | */ |
| 14 | enum { |
| 15 | C_STATE_C1, /* 0 */ |
| 16 | C_STATE_C3, /* 1 */ |
| 17 | C_STATE_C6, /* 2 */ |
| 18 | C_STATE_C7, /* 3 */ |
| 19 | NUM_C_STATES |
| 20 | }; |
| 21 | |
| 22 | static const acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 23 | [C_STATE_C1] = { |
| 24 | /* C1 */ |
| 25 | .latency = 1, |
| 26 | .power = 0x3e8, |
| 27 | .resource = MWAIT_RES(0, 0), |
| 28 | }, |
| 29 | [C_STATE_C3] = { |
| 30 | /* C3 */ |
| 31 | .latency = 15, |
| 32 | .power = 0x1f4, |
| 33 | .resource = MWAIT_RES(1, 0), |
| 34 | }, |
| 35 | [C_STATE_C6] = { |
| 36 | /* C6 */ |
| 37 | .latency = 41, |
| 38 | .power = 0x15e, |
| 39 | .resource = MWAIT_RES(2, 0), |
| 40 | }, |
| 41 | [C_STATE_C7] = { |
| 42 | /* C7 */ |
| 43 | .latency = 41, |
| 44 | .power = 0x0c8, |
| 45 | .resource = MWAIT_RES(3, 0), |
| 46 | } |
| 47 | }; |
| 48 | |
| 49 | /* Max states supported */ |
| 50 | static int cstate_set_all[] = { |
| 51 | C_STATE_C1, |
| 52 | C_STATE_C3, |
| 53 | C_STATE_C6, |
| 54 | C_STATE_C7 |
| 55 | }; |
| 56 | |
| 57 | static int cstate_set_c1_c6[] = { |
| 58 | C_STATE_C1, |
| 59 | C_STATE_C6, |
| 60 | }; |
| 61 | |
Angel Pons | e9f10ff | 2021-10-17 13:28:23 +0200 | [diff] [blame] | 62 | const acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Marc Jones | 9f55574 | 2020-09-24 16:35:56 -0600 | [diff] [blame] | 63 | { |
Marc Jones | 31ed885 | 2021-01-15 13:29:14 -0700 | [diff] [blame] | 64 | static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)]; |
| 65 | int *cstate_set; |
| 66 | int i; |
| 67 | |
| 68 | const config_t *config = config_of_soc(); |
| 69 | |
| 70 | const enum acpi_cstate_mode states = config->cstate_states; |
| 71 | |
| 72 | switch (states) { |
| 73 | case CSTATES_C1C6: |
| 74 | *entries = ARRAY_SIZE(cstate_set_c1_c6); |
| 75 | cstate_set = cstate_set_c1_c6; |
| 76 | break; |
| 77 | case CSTATES_ALL: |
| 78 | default: |
| 79 | *entries = ARRAY_SIZE(cstate_set_all); |
| 80 | cstate_set = cstate_set_all; |
| 81 | break; |
| 82 | } |
| 83 | |
| 84 | for (i = 0; i < *entries; i++) { |
| 85 | map[i] = cstate_map[cstate_set[i]]; |
| 86 | map[i].ctype = i + 1; |
| 87 | } |
| 88 | return map; |
Marc Jones | 9f55574 | 2020-09-24 16:35:56 -0600 | [diff] [blame] | 89 | } |
| 90 | |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 91 | static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1]; |
Arthur Heymans | c7eebac | 2020-11-06 12:25:28 +0100 | [diff] [blame] | 92 | |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 93 | size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) |
Marc Jones | 9f55574 | 2020-09-24 16:35:56 -0600 | [diff] [blame] | 94 | { |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 95 | int index = 0; |
Arthur Heymans | 7598b4b | 2020-11-06 12:33:35 +0100 | [diff] [blame] | 96 | const IIO_UDS *hob = get_iio_uds(); |
Marc Jones | 9f55574 | 2020-09-24 16:35:56 -0600 | [diff] [blame] | 97 | |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 98 | *ioapic_bases = xeonsp_ioapic_bases; |
Christian Walter | 106def9 | 2022-06-29 18:23:51 +0200 | [diff] [blame] | 99 | |
Patrick Rudolph | ac02857 | 2023-07-14 17:44:33 +0200 | [diff] [blame] | 100 | for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; socket++) { |
| 101 | if (!soc_cpu_is_enabled(socket)) |
| 102 | continue; |
| 103 | iio++; |
Arthur Heymans | 7598b4b | 2020-11-06 12:33:35 +0100 | [diff] [blame] | 104 | for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { |
| 105 | const STACK_RES *ri = |
| 106 | &hob->PlatformData.IIO_resource[socket].StackRes[stack]; |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 107 | uint32_t ioapic_base = ri->IoApicBase; |
Arthur Heymans | 470f1d3 | 2023-08-31 18:19:09 +0200 | [diff] [blame] | 108 | if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF) |
| 109 | continue; |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 110 | assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); |
| 111 | xeonsp_ioapic_bases[index++] = ioapic_base; |
| 112 | if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC)) |
| 113 | return index; |
Arthur Heymans | 7598b4b | 2020-11-06 12:33:35 +0100 | [diff] [blame] | 114 | /* |
| 115 | * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. |
Arthur Heymans | 77038b1 | 2020-11-06 12:59:46 +0100 | [diff] [blame] | 116 | * The IIO IOAPIC is placed at 0x1000 from the reported base. |
Arthur Heymans | 7598b4b | 2020-11-06 12:33:35 +0100 | [diff] [blame] | 117 | */ |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 118 | if (socket == 0 && stack == 0) { |
| 119 | ioapic_base += 0x1000; |
| 120 | assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); |
| 121 | xeonsp_ioapic_bases[index++] = ioapic_base; |
| 122 | } |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 123 | } |
| 124 | } |
Marc Jones | 9f55574 | 2020-09-24 16:35:56 -0600 | [diff] [blame] | 125 | |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 126 | return index; |
Marc Jones | 9f55574 | 2020-09-24 16:35:56 -0600 | [diff] [blame] | 127 | } |