Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 14 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 15 | #include <device/pci_ops.h> |
Arthur Heymans | e27c013 | 2019-11-12 23:34:13 +0100 | [diff] [blame] | 16 | #include "i945.h" |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 17 | |
Arthur Heymans | e27c013 | 2019-11-12 23:34:13 +0100 | [diff] [blame] | 18 | void bootblock_early_northbridge_init(void) |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 19 | { |
| 20 | uint32_t reg; |
| 21 | |
| 22 | /* |
| 23 | * The "io" variant of the config access is explicitly used to |
Elyes HAOUAS | 96184e9 | 2018-05-09 21:23:25 +0200 | [diff] [blame] | 24 | * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true. |
| 25 | * That way all subsequent non-explicit config accesses use |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 26 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 27 | * the first thing called in the non-asm boot block code. The final |
| 28 | * assumption is that no assembly code is using the |
Elyes HAOUAS | 0c9630e | 2020-01-07 20:06:08 +0100 | [diff] [blame^] | 29 | * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 30 | * |
| 31 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 32 | * 4GiB. |
| 33 | */ |
| 34 | reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 35 | pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 36 | } |