efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <arch/smp/mpspec.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <string.h> |
| 26 | #include <stdint.h> |
| 27 | #include <arch/cpu.h> |
| 28 | #include <cpu/x86/lapic.h> |
| 29 | #include <cpu/amd/amdfam10_sysconf.h> |
| 30 | |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 31 | extern u8 bus_sp5100[2]; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 32 | |
| 33 | static void *smp_write_config_table(void *v) |
| 34 | { |
| 35 | struct mp_config_table *mc; |
Kyösti Mälkki | da6d8b1 | 2014-07-21 18:45:14 +0300 | [diff] [blame] | 36 | int bus_isa; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 37 | u32 apicid_sp5100; |
| 38 | u32 apicid_sr5650; |
| 39 | device_t dev; |
| 40 | u32 dword; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 41 | |
| 42 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
Patrick Georgi | c8feedd | 2012-02-16 18:43:25 +0100 | [diff] [blame] | 43 | mptable_init(mc, LOCAL_APIC_ADDR); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 44 | |
| 45 | smp_write_processors(mc); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 46 | mptable_write_buses(mc, NULL, &bus_isa); |
| 47 | |
| 48 | /* |
| 49 | * AGESA v5 Apply apic enumeration rules |
| 50 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 51 | * put the local-APICs at m..z |
| 52 | * For systems with < 16 APICs, put the Local-APICs at 0..n and |
| 53 | * put the IO-APICs at (n + 1)..z |
| 54 | */ |
Kyösti Mälkki | a6c525a | 2014-04-16 09:43:40 +0300 | [diff] [blame] | 55 | if (CONFIG_MAX_CPUS >= 16) |
| 56 | apicid_sp5100 = 0x0; |
| 57 | else |
| 58 | apicid_sp5100 = CONFIG_MAX_CPUS + 1; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 59 | apicid_sr5650 = apicid_sp5100 + 1; |
| 60 | |
Kyösti Mälkki | 0c797f1 | 2014-07-21 19:35:16 +0300 | [diff] [blame^] | 61 | dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 62 | if (dev) { |
| 63 | /* Set SP5100 IOAPIC ID */ |
| 64 | dword = pci_read_config32(dev, 0x74) & 0xfffffff0; |
| 65 | smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); |
| 66 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 67 | #ifdef UNUSED_CODE |
| 68 | u8 byte; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 69 | /* Initialize interrupt mapping */ |
| 70 | /* aza */ |
| 71 | byte = pci_read_config8(dev, 0x63); |
| 72 | byte &= 0xf8; |
| 73 | byte |= 0; /* 0: INTA, ...., 7: INTH */ |
| 74 | pci_write_config8(dev, 0x63, byte); |
| 75 | /* SATA */ |
| 76 | dword = pci_read_config32(dev, 0xAC); |
| 77 | dword &= ~(7 << 26); |
| 78 | dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ |
| 79 | /* dword |= 1<<22; PIC and APIC co exists */ |
| 80 | pci_write_config32(dev, 0xAC, dword); |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 81 | #endif |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 82 | |
| 83 | /* |
| 84 | * 00:12.0: PROG SATA : INT F |
| 85 | * 00:13.0: INTA USB_0 |
| 86 | * 00:13.1: INTB USB_1 |
| 87 | * 00:13.2: INTC USB_2 |
| 88 | * 00:13.3: INTD USB_3 |
| 89 | * 00:13.4: INTC USB_4 |
| 90 | * 00:13.5: INTD USB2 |
| 91 | * 00:14.1: INTA IDE |
| 92 | * 00:14.2: Prog HDA : INT E |
| 93 | * 00:14.5: INTB ACI |
| 94 | * 00:14.6: INTB MCI |
| 95 | */ |
| 96 | |
| 97 | /* Set RS5650 IOAPIC ID */ |
| 98 | dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 99 | if (dev) { |
| 100 | pci_write_config32(dev, 0xF8, 0x1); |
| 101 | dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; |
| 102 | smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); |
| 103 | } |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 104 | |
| 105 | } |
| 106 | |
| 107 | /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 108 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 109 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
| 110 | |
| 111 | mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); |
| 112 | |
| 113 | /* PCI interrupts are level triggered, and are |
| 114 | * associated with a specific bus/device/function tuple. |
| 115 | */ |
| 116 | #define PCI_INT(bus, dev, int_sign, pin) \ |
| 117 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin)) |
| 118 | |
| 119 | /* SMBUS */ |
| 120 | //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 |
| 121 | |
| 122 | /* HD Audio */ |
| 123 | PCI_INT(0x0, 0x14, 0x2, 0x10); |
| 124 | |
| 125 | /* USB */ |
| 126 | /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ |
| 127 | /* EHCI hard-wired to 02h, corresponding to using INTB# */ |
| 128 | /* USB1 */ |
| 129 | PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ |
| 130 | PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ |
| 131 | PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ |
| 132 | |
| 133 | /* USB2 */ |
| 134 | PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ |
| 135 | PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ |
| 136 | PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ |
| 137 | |
| 138 | /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ |
| 139 | PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ |
| 140 | |
| 141 | /* SATA */ |
| 142 | PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG |
| 143 | |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 144 | /* PCI slots */ |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 145 | /* PCI_SLOT 0. */ |
| 146 | PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); |
| 147 | PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); |
| 148 | PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); |
| 149 | PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 150 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 151 | /* PCI_SLOT 1. */ |
| 152 | PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); |
| 153 | PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); |
| 154 | PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); |
| 155 | PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 156 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 157 | /* PCI_SLOT 2. */ |
| 158 | PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); |
| 159 | PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); |
| 160 | PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); |
| 161 | PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 162 | |
| 163 | |
| 164 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 165 | IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); |
| 166 | IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); |
| 167 | /* There is no extension information... */ |
| 168 | |
| 169 | /* Compute the checksums */ |
Patrick Georgi | b0a9c5c | 2011-10-07 23:01:55 +0200 | [diff] [blame] | 170 | return mptable_finalize(mc); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | unsigned long write_smp_table(unsigned long addr) |
| 174 | { |
| 175 | void *v; |
Patrick Georgi | c75c79b | 2011-10-07 22:41:07 +0200 | [diff] [blame] | 176 | v = smp_write_floating_table(addr, 0); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 177 | return (unsigned long)smp_write_config_table(v); |
| 178 | } |