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review.coreboot.org / coreboot / 0c797f1c28cd16c64482b2cea554e89baaa31445 / . / src / mainboard / amd / dinar / irq_tables.c
blob: 8242b4e911a2d1a1c58efe0d49ee9a25bf7fec6a [file] [log] [blame]
Kerry Sheh6d6d18e2012-02-07 20:32:34 +0800[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +0100[diff] [blame]17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Kerry Sheh6d6d18e2012-02-07 20:32:34 +0800[diff] [blame]18 */
19
20
21#include <console/console.h>
22#include <device/pci.h>
23#include <string.h>
24#include <stdint.h>
25#include <arch/pirq_routing.h>
Bruce Griffith93b57c52013-06-25 19:27:17 -0600[diff] [blame]26#include <cpu/amd/amdfam15.h>
Kerry Sheh6d6d18e2012-02-07 20:32:34 +0800[diff] [blame]27
28static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
29 u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
30 u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
31 u8 slot, u8 rfu)
32{
33 pirq_info->bus = bus;
34 pirq_info->devfn = devfn;
35 pirq_info->irq[0].link = link0;
36 pirq_info->irq[0].bitmap = bitmap0;
37 pirq_info->irq[1].link = link1;
38 pirq_info->irq[1].bitmap = bitmap1;
39 pirq_info->irq[2].link = link2;
40 pirq_info->irq[2].bitmap = bitmap2;
41 pirq_info->irq[3].link = link3;
42 pirq_info->irq[3].bitmap = bitmap3;
43 pirq_info->slot = slot;
44 pirq_info->rfu = rfu;
45}
Kerry Sheh6d6d18e2012-02-07 20:32:34 +0800[diff] [blame]46
47unsigned long write_pirq_routing_table(unsigned long addr)
48{
49
50 struct irq_routing_table *pirq;
51 struct irq_info *pirq_info;
52 u32 slot_num;
53 u8 *v;
54
55 u8 sum = 0;
56 int i;
57
Kerry Sheh6d6d18e2012-02-07 20:32:34 +0800[diff] [blame]58 /* Align the table to be 16 byte aligned. */
59 addr += 15;
60 addr &= ~15;
61
Kyösti Mälkki9533d832014-06-26 05:30:54 +0300[diff] [blame]62 /* This table must be between 0xf0000 & 0x100000 */
Kerry Sheh6d6d18e2012-02-07 20:32:34 +0800[diff] [blame]63 printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
64
65 pirq = (void *)(addr);
66 v = (u8 *) (addr);
67
68 pirq->signature = PIRQ_SIGNATURE;
69 pirq->version = PIRQ_VERSION;
70
Kyösti Mälkki0c797f12014-07-21 19:35:16 +0300[diff] [blame^]71 pirq->rtr_bus = 0;
72 pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
Kerry Sheh6d6d18e2012-02-07 20:32:34 +0800[diff] [blame]73
74 pirq->exclusive_irqs = 0;
75
76 pirq->rtr_vendor = 0x1002;
77 pirq->rtr_device = 0x4384;
78
79 pirq->miniport_data = 0;
80
81 memset(pirq->rfu, 0, sizeof(pirq->rfu));
82
83 pirq_info = (void *)(&pirq->checksum + 1);
84 slot_num = 0;
85
86
87 /* pci bridge */
Kyösti Mälkki0c797f12014-07-21 19:35:16 +0300[diff] [blame^]88 write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
Kerry Sheh6d6d18e2012-02-07 20:32:34 +0800[diff] [blame]89 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
90 0);
91 pirq_info++;
92
93
94
95 slot_num++;
96
97
98
99 pirq->size = 32 + 16 * slot_num;
100
101 for (i = 0; i < pirq->size; i++)
102 sum += v[i];
103
104 sum = pirq->checksum - sum;
105
106 if (sum != pirq->checksum) {
107 pirq->checksum = sum;
108 }
109
110 printk(BIOS_INFO, "write_pirq_routing_table done.\n");
111
112 return (unsigned long)pirq_info;
113
114}