Angel Pons | 0c0b16a | 2020-03-19 10:56:18 +0100 | [diff] [blame^] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | ## This file is part of the coreboot project. |
| 3 | |
| 4 | chip northbridge/intel/sandybridge |
| 5 | device cpu_cluster 0 on |
| 6 | chip cpu/intel/model_206ax |
| 7 | register "c1_acpower" = "1" |
| 8 | register "c1_battery" = "1" |
| 9 | register "c2_acpower" = "3" |
| 10 | register "c2_battery" = "3" |
| 11 | register "c3_acpower" = "5" |
| 12 | register "c3_battery" = "5" |
| 13 | device lapic 0 on end |
| 14 | device lapic 0xacac off end |
| 15 | end |
| 16 | end |
| 17 | register "pci_mmio_size" = "2048" |
| 18 | device domain 0 on |
| 19 | subsystemid 0x1458 0x5000 inherit |
| 20 | |
| 21 | device pci 00.0 on end # Host bridge |
| 22 | device pci 01.0 on end # PEG |
| 23 | device pci 02.0 on end # iGPU |
| 24 | |
| 25 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
| 26 | register "c2_latency" = "0x0065" |
| 27 | register "gen1_dec" = "0x003c0a01" |
| 28 | register "sata_interface_speed_support" = "0x3" |
| 29 | register "sata_port_map" = "0x33" |
| 30 | register "spi_lvscc" = "0x2005" |
| 31 | register "spi_uvscc" = "0x2005" |
| 32 | |
| 33 | device pci 16.0 on end # MEI #1 |
| 34 | device pci 1a.0 on end # USB2 EHCI #2 |
| 35 | device pci 1b.0 on end # HD Audio |
| 36 | |
| 37 | device pci 1d.0 on end # USB2 EHCI #1 |
| 38 | device pci 1e.0 off end # PCI bridge |
| 39 | device pci 1f.0 on end # LPC bridge |
| 40 | device pci 1f.2 on end # SATA Controller 1 |
| 41 | device pci 1f.3 on end # SMBus |
| 42 | device pci 1f.5 off end # SATA Controller 2 |
| 43 | device pci 1f.6 on end # Thermal |
| 44 | end |
| 45 | end |
| 46 | end |