Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 6e5f909830899fc7c2a2882c0d1278309fca688a / . / src / northbridge / intel / x4x / acpi / hostbridge.asl
blob: 9a5cbd9618bb7c55f215dcaf821eab7721ee2c0a [file] [log] [blame]
Angel Pons4b429832020-04-02 23:48:50 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Damien Zammit43a1f782015-08-19 15:16:59 +1000[diff] [blame]2
3#include <arch/ioapic.h>
4
5Name(_HID,EISAID("PNP0A08")) // PCIe
6Name(_CID,EISAID("PNP0A03")) // PCI
7
Damien Zammit43a1f782015-08-19 15:16:59 +1000[diff] [blame]8Name(_BBN, 0)
9
10Device (MCHC)
11{
12 Name(_ADR, 0x00000000) // 0:0.0
13
14 OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
15 Field (MCHP, DWordAcc, NoLock, Preserve)
16 {
17 Offset (0x40), // EPBAR
18 EPEN, 1, // Enable
19 , 11, //
20 EPBR, 24, // EPBAR
21
22 Offset (0x48), // MCHBAR
23 MHEN, 1, // Enable
24 , 13, //
25 MHBR, 22, // MCHBAR
26
27 Offset (0x60), // PCIe BAR
28 PXEN, 1, // Enable
29 PXSZ, 2, // BAR size
30 , 23, //
31 PXBR, 10, // PCIe BAR
32
33 Offset (0x68), // DMIBAR
34 DMEN, 1, // Enable
35 , 11, //
36 DMBR, 24, // DMIBAR
37
38 // ...
39
40 Offset (0x90), // PAM0
41 , 4,
42 PM0H, 2,
43 , 2,
44 Offset (0x91), // PAM1
45 PM1L, 2,
46 , 2,
47 PM1H, 2,
48 , 2,
49 Offset (0x92), // PAM2
50 PM2L, 2,
51 , 2,
52 PM2H, 2,
53 , 2,
54 Offset (0x93), // PAM3
55 PM3L, 2,
56 , 2,
57 PM3H, 2,
58 , 2,
59 Offset (0x94), // PAM4
60 PM4L, 2,
61 , 2,
62 PM4H, 2,
63 , 2,
64 Offset (0x95), // PAM5
65 PM5L, 2,
66 , 2,
67 PM5H, 2,
68 , 2,
69 Offset (0x96), // PAM6
70 PM6L, 2,
71 , 2,
72 PM6H, 2,
73 , 2,
74
75 Offset (0xa0), // Top of Used Memory
76 TOM, 8,
77
78 Offset (0xb0), // Top of Low Used Memory
79 , 4,
80 TLUD, 12,
81 }
82
83}
84
85Name (MCRS, ResourceTemplate()
86{
87 // Bus Numbers
88 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
89 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
90
91 // IO Region 0
92 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
93 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
94
95 // PCI Config Space
96 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
97
98 // IO Region 1
99 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
100 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
101
102 // VGA memory (0xa0000-0xbffff)
103 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
104 Cacheable, ReadWrite,
105 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
106 0x00020000,,, ASEG)
107
108 // OPROM reserved (0xc0000-0xc3fff)
109 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
110 Cacheable, ReadWrite,
111 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
112 0x00004000,,, OPR0)
113
114 // OPROM reserved (0xc4000-0xc7fff)
115 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
116 Cacheable, ReadWrite,
117 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
118 0x00004000,,, OPR1)
119
120 // OPROM reserved (0xc8000-0xcbfff)
121 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
122 Cacheable, ReadWrite,
123 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
124 0x00004000,,, OPR2)
125
126 // OPROM reserved (0xcc000-0xcffff)
127 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
128 Cacheable, ReadWrite,
129 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
130 0x00004000,,, OPR3)
131
132 // OPROM reserved (0xd0000-0xd3fff)
133 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
134 Cacheable, ReadWrite,
135 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
136 0x00004000,,, OPR4)
137
138 // OPROM reserved (0xd4000-0xd7fff)
139 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
140 Cacheable, ReadWrite,
141 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
142 0x00004000,,, OPR5)
143
144 // OPROM reserved (0xd8000-0xdbfff)
145 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
146 Cacheable, ReadWrite,
147 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
148 0x00004000,,, OPR6)
149
150 // OPROM reserved (0xdc000-0xdffff)
151 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
152 Cacheable, ReadWrite,
153 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
154 0x00004000,,, OPR7)
155
156 // BIOS Extension (0xe0000-0xe3fff)
157 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
158 Cacheable, ReadWrite,
159 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
160 0x00004000,,, ESG0)
161
162 // BIOS Extension (0xe4000-0xe7fff)
163 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
164 Cacheable, ReadWrite,
165 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
166 0x00004000,,, ESG1)
167
168 // BIOS Extension (0xe8000-0xebfff)
169 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
170 Cacheable, ReadWrite,
171 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
172 0x00004000,,, ESG2)
173
174 // BIOS Extension (0xec000-0xeffff)
175 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
176 Cacheable, ReadWrite,
177 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
178 0x00004000,,, ESG3)
179
180 // System BIOS (0xf0000-0xfffff)
181 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
182 Cacheable, ReadWrite,
183 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
184 0x00010000,,, FSEG)
185
186 // PCI Memory Region (Top of memory-0xfebfffff)
187 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
188 Cacheable, ReadWrite,
189 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
190 IO_APIC_ADDR,,, PM01)
191
192 // TPM Area (0xfed40000-0xfed44fff)
193 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
194 Cacheable, ReadWrite,
195 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
196 0x00005000,,, TPMR)
197})
198
199// Current Resource Settings
200
201Method (_CRS, 0, Serialized)
202{
203 // Find PCI resource area in MCRS
204 CreateDwordField(MCRS, ^PM01._MIN, PMIN)
205 CreateDwordField(MCRS, ^PM01._MAX, PMAX)
206 CreateDwordField(MCRS, ^PM01._LEN, PLEN)
207
208 // Fix up PCI memory region:
209 // Enter actual TOLUD. The TOLUD register contains bits 20-31 of
210 // the top of memory address.
211 ShiftLeft (^MCHC.TLUD, 20, PMIN)
212 Add(Subtract(PMAX, PMIN), 1, PLEN)
213
214 Return (MCRS)
215}