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review.coreboot.org / coreboot / 0b29a7b37c19200516dadc5c4bf0a1eb9d1290ec / . / src / drivers / gic / gic.c
blob: 885d2216be280f09739561edd62959b32a79a3b2 [file] [log] [blame]
Aaron Durbin27ce0942014-09-11 16:07:02 -0500[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <arch/cpu.h>
21#include <arch/io.h>
22#include <console/console.h>
23#include <gic.h>
24#include "gic.h"
25
26enum {
27 ENABLE_GRP0 = 0x1 << 0,
28 ENABLE_GRP1 = 0x1 << 1,
29};
30
31struct gic {
32 struct gicd_mmio *gicd;
33 struct gicc_mmio *gicc;
34 size_t num_interrupts;
35 unsigned int version;
36 unsigned int security_extensions;
37};
38
39static struct gic *gic_get(void)
40{
41 static struct gic gic;
42
43 if (gic.gicd == NULL) {
44 uint32_t typer;
45
46 gic.gicd = gicd_base();
47 gic.gicc = gicc_base();
48 typer = read32(&gic.gicd->typer);
49 gic.num_interrupts = 32 * ((typer & 0x1f) + 1);
50 gic.security_extensions = !!(typer & (1 << 10));
51 gic.version = (read32(&gic.gicd->icpidr2) & 0xf0) >> 4;
52
53 printk(BIOS_DEBUG, "GICv%d - %zu ints %s GICD=%p GICC=%p\n",
54 gic.version, gic.num_interrupts,
55 gic.security_extensions ? "SecExtn" : "",
56 gic.gicd, gic.gicc);
57 }
58
59 return &gic;
60}
61
62static inline void gic_write(uint32_t *base, uint32_t val)
63{
64 write32(val, base);
65}
66
67static void gic_write_regs(uint32_t *base, size_t num_regs, uint32_t val)
68{
69 size_t i;
70
71 for (i = 0; i < num_regs; i++)
72 gic_write(base++, val);
73}
74
75static void gic_write_banked_regs(uint32_t *base, size_t interrupts_per_reg,
76 uint32_t val)
77{
78 /* 1st 32 interrupts are banked per CPU. */
79 gic_write_regs(base, 32 / interrupts_per_reg, val);
80}
81
82void gic_init(void)
83{
84 struct gic *gic;
85 struct gicd_mmio *gicd;
86 struct gicc_mmio *gicc;
87 uint32_t cpu_mask;
88
89 gic = gic_get();
90 gicd = gic->gicd;
91 gicc = gic->gicc;
92
93 /* Enable Group 0 and Group 1 in GICD -- banked regs. */
94 gic_write(&gicd->ctlr, ENABLE_GRP0 | ENABLE_GRP1);
95
96 /* Enable Group 0 and Group 1 in GICC and enable all priroity levels. */
97 gic_write(&gicc->ctlr, ENABLE_GRP0 | ENABLE_GRP1);
98 gic_write(&gicc->pmr, 1 << 7);
99
100 cpu_mask = 1 << smp_processor_id();
101 cpu_mask |= cpu_mask << 8;
102 cpu_mask |= cpu_mask << 16;
103
104 /* Only write banked registers for secondary CPUs. */
105 if (smp_processor_id()) {
106 gic_write_banked_regs(&gicd->itargetsr[0], 4, cpu_mask);
107 /* Put interrupts into Group 1. */
108 gic_write_banked_regs(&gicd->igroupr[0], 32, ~0x0);
109 /* Allow Non-secure access to everything. */
110 gic_write_banked_regs(&gicd->nsacr[0], 16, ~0x0);
111 return;
112 }
113
114 /* All interrupts routed to processors that execute this function. */
115 gic_write_regs(&gicd->itargetsr[0], gic->num_interrupts / 4, cpu_mask);
116 /* Put all interrupts into Gropup 1. */
117 gic_write_regs(&gicd->igroupr[0], gic->num_interrupts / 32, ~0x0);
118 /* Allow Non-secure access to everything. */
119 gic_write_regs(&gicd->nsacr[0], gic->num_interrupts / 16, ~0x0);
120}