Macpaul Lin | 5d16f8d | 2022-08-11 16:27:10 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 2 | |
| 3 | #include <assert.h> |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 4 | #include <soc/mcu_common.h> |
| 5 | #include <soc/spm.h> |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 6 | |
| 7 | static const struct pwr_ctrl spm_init_ctrl = { |
| 8 | .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS | |
| 9 | SPM_FLAG_RUN_COMMON_SCENARIO, |
| 10 | |
| 11 | /* SPM_AP_STANDBY_CON */ |
| 12 | /* [0] */ |
| 13 | .reg_wfi_op = 0, |
| 14 | /* [1] */ |
| 15 | .reg_wfi_type = 0, |
| 16 | /* [2] */ |
| 17 | .reg_mp0_cputop_idle_mask = 0, |
| 18 | /* [3] */ |
| 19 | .reg_mp1_cputop_idle_mask = 0, |
| 20 | /* [4] */ |
| 21 | .reg_mcusys_idle_mask = 0, |
| 22 | /* [25] */ |
| 23 | .reg_md_apsrc_1_sel = 0, |
| 24 | /* [26] */ |
| 25 | .reg_md_apsrc_0_sel = 0, |
| 26 | /* [29] */ |
| 27 | .reg_conn_apsrc_sel = 0, |
| 28 | |
| 29 | /* SPM_SRC_REQ */ |
| 30 | /* [0] */ |
| 31 | .reg_spm_apsrc_req = 0, |
| 32 | /* [1] */ |
| 33 | .reg_spm_f26m_req = 0, |
| 34 | /* [3] */ |
| 35 | .reg_spm_infra_req = 0, |
| 36 | /* [4] */ |
| 37 | .reg_spm_vrf18_req = 0, |
| 38 | /* [7] FIXME: default disable HW Auto S1*/ |
| 39 | .reg_spm_ddr_en_req = 1, |
| 40 | /* [8] */ |
| 41 | .reg_spm_dvfs_req = 0, |
| 42 | /* [9] */ |
| 43 | .reg_spm_sw_mailbox_req = 0, |
| 44 | /* [10] */ |
| 45 | .reg_spm_sspm_mailbox_req = 0, |
| 46 | /* [11] */ |
| 47 | .reg_spm_adsp_mailbox_req = 0, |
| 48 | /* [12] */ |
| 49 | .reg_spm_scp_mailbox_req = 0, |
| 50 | |
| 51 | /* SPM_SRC_MASK */ |
| 52 | /* [0] */ |
| 53 | .reg_sspm_srcclkena_0_mask_b = 1, |
| 54 | /* [1] */ |
| 55 | .reg_sspm_infra_req_0_mask_b = 1, |
| 56 | /* [2] */ |
| 57 | .reg_sspm_apsrc_req_0_mask_b = 1, |
| 58 | /* [3] */ |
| 59 | .reg_sspm_vrf18_req_0_mask_b = 1, |
| 60 | /* [4] */ |
| 61 | .reg_sspm_ddr_en_0_mask_b = 1, |
| 62 | /* [5] */ |
| 63 | .reg_scp_srcclkena_mask_b = 1, |
| 64 | /* [6] */ |
| 65 | .reg_scp_infra_req_mask_b = 1, |
| 66 | /* [7] */ |
| 67 | .reg_scp_apsrc_req_mask_b = 1, |
| 68 | /* [8] */ |
| 69 | .reg_scp_vrf18_req_mask_b = 1, |
| 70 | /* [9] */ |
| 71 | .reg_scp_ddr_en_mask_b = 1, |
| 72 | /* [10] */ |
| 73 | .reg_audio_dsp_srcclkena_mask_b = 1, |
| 74 | /* [11] */ |
| 75 | .reg_audio_dsp_infra_req_mask_b = 1, |
| 76 | /* [12] */ |
| 77 | .reg_audio_dsp_apsrc_req_mask_b = 1, |
| 78 | /* [13] */ |
| 79 | .reg_audio_dsp_vrf18_req_mask_b = 1, |
| 80 | /* [14] */ |
| 81 | .reg_audio_dsp_ddr_en_mask_b = 1, |
| 82 | /* [15] */ |
| 83 | .reg_apu_srcclkena_mask_b = 1, |
| 84 | /* [16] */ |
| 85 | .reg_apu_infra_req_mask_b = 1, |
| 86 | /* [17] */ |
| 87 | .reg_apu_apsrc_req_mask_b = 1, |
| 88 | /* [18] */ |
| 89 | .reg_apu_vrf18_req_mask_b = 1, |
| 90 | /* [19] */ |
| 91 | .reg_apu_ddr_en_mask_b = 1, |
| 92 | /* [20] */ |
| 93 | .reg_cpueb_srcclkena_mask_b = 1, |
| 94 | /* [21] */ |
| 95 | .reg_cpueb_infra_req_mask_b = 1, |
| 96 | /* [22] */ |
| 97 | .reg_cpueb_apsrc_req_mask_b = 1, |
| 98 | /* [23] */ |
| 99 | .reg_cpueb_vrf18_req_mask_b = 1, |
| 100 | /* [24] */ |
| 101 | .reg_cpueb_ddr_en_mask_b = 1, |
| 102 | /* [25] */ |
| 103 | .reg_bak_psri_srcclkena_mask_b = 0, |
| 104 | /* [26] */ |
| 105 | .reg_bak_psri_infra_req_mask_b = 0, |
| 106 | /* [27] */ |
| 107 | .reg_bak_psri_apsrc_req_mask_b = 0, |
| 108 | /* [28] */ |
| 109 | .reg_bak_psri_vrf18_req_mask_b = 0, |
| 110 | /* [29] */ |
| 111 | .reg_bak_psri_ddr_en_mask_b = 0, |
| 112 | |
| 113 | /* SPM_SRC2_MASK */ |
| 114 | /* [0] */ |
| 115 | .reg_msdc0_srcclkena_mask_b = 1, |
| 116 | /* [1] */ |
| 117 | .reg_msdc0_infra_req_mask_b = 1, |
| 118 | /* [2] */ |
| 119 | .reg_msdc0_apsrc_req_mask_b = 1, |
| 120 | /* [3] */ |
| 121 | .reg_msdc0_vrf18_req_mask_b = 1, |
| 122 | /* [4] */ |
| 123 | .reg_msdc0_ddr_en_mask_b = 1, |
| 124 | /* [5] */ |
| 125 | .reg_msdc1_srcclkena_mask_b = 1, |
| 126 | /* [6] */ |
| 127 | .reg_msdc1_infra_req_mask_b = 1, |
| 128 | /* [7] */ |
| 129 | .reg_msdc1_apsrc_req_mask_b = 1, |
| 130 | /* [8] */ |
| 131 | .reg_msdc1_vrf18_req_mask_b = 1, |
| 132 | /* [9] */ |
| 133 | .reg_msdc1_ddr_en_mask_b = 1, |
| 134 | /* [10] */ |
| 135 | .reg_msdc2_srcclkena_mask_b = 1, |
| 136 | /* [11] */ |
| 137 | .reg_msdc2_infra_req_mask_b = 1, |
| 138 | /* [12] */ |
| 139 | .reg_msdc2_apsrc_req_mask_b = 1, |
| 140 | /* [13] */ |
| 141 | .reg_msdc2_vrf18_req_mask_b = 1, |
| 142 | /* [14] */ |
| 143 | .reg_msdc2_ddr_en_mask_b = 1, |
| 144 | /* [15] */ |
| 145 | .reg_ufs_srcclkena_mask_b = 1, |
| 146 | /* [16] */ |
| 147 | .reg_ufs_infra_req_mask_b = 1, |
| 148 | /* [17] */ |
| 149 | .reg_ufs_apsrc_req_mask_b = 1, |
| 150 | /* [18] */ |
| 151 | .reg_ufs_vrf18_req_mask_b = 1, |
| 152 | /* [19] */ |
| 153 | .reg_ufs_ddr_en_mask_b = 1, |
| 154 | /* [20] */ |
| 155 | .reg_usb_srcclkena_mask_b = 1, |
| 156 | /* [21] */ |
| 157 | .reg_usb_infra_req_mask_b = 1, |
| 158 | /* [22] */ |
| 159 | .reg_usb_apsrc_req_mask_b = 1, |
| 160 | /* [23] */ |
| 161 | .reg_usb_vrf18_req_mask_b = 1, |
| 162 | /* [24] */ |
| 163 | .reg_usb_ddr_en_mask_b = 1, |
| 164 | /* [25] */ |
| 165 | .reg_pextp_p0_srcclkena_mask_b = 1, |
| 166 | /* [26] */ |
| 167 | .reg_pextp_p0_infra_req_mask_b = 1, |
| 168 | /* [27] */ |
| 169 | .reg_pextp_p0_apsrc_req_mask_b = 1, |
| 170 | /* [28] */ |
| 171 | .reg_pextp_p0_vrf18_req_mask_b = 1, |
| 172 | /* [29] */ |
| 173 | .reg_pextp_p0_ddr_en_mask_b = 1, |
| 174 | |
| 175 | /* SPM_SRC3_MASK */ |
| 176 | /* [0] */ |
| 177 | .reg_pextp_p1_srcclkena_mask_b = 1, |
| 178 | /* [1] */ |
| 179 | .reg_pextp_p1_infra_req_mask_b = 1, |
| 180 | /* [2] */ |
| 181 | .reg_pextp_p1_apsrc_req_mask_b = 1, |
| 182 | /* [3] */ |
| 183 | .reg_pextp_p1_vrf18_req_mask_b = 1, |
| 184 | /* [4] */ |
| 185 | .reg_pextp_p1_ddr_en_mask_b = 1, |
| 186 | /* [5] */ |
| 187 | .reg_gce0_infra_req_mask_b = 1, |
| 188 | /* [6] */ |
| 189 | .reg_gce0_apsrc_req_mask_b = 1, |
| 190 | /* [7] */ |
| 191 | .reg_gce0_vrf18_req_mask_b = 1, |
| 192 | /* [8] */ |
| 193 | .reg_gce0_ddr_en_mask_b = 1, |
| 194 | /* [9] */ |
| 195 | .reg_gce1_infra_req_mask_b = 1, |
| 196 | /* [10] */ |
| 197 | .reg_gce1_apsrc_req_mask_b = 1, |
| 198 | /* [11] */ |
| 199 | .reg_gce1_vrf18_req_mask_b = 1, |
| 200 | /* [12] */ |
| 201 | .reg_gce1_ddr_en_mask_b = 1, |
| 202 | /* [13] */ |
| 203 | .reg_spm_srcclkena_reserved_mask_b = 1, |
| 204 | /* [14] */ |
| 205 | .reg_spm_infra_req_reserved_mask_b = 1, |
| 206 | /* [15] */ |
| 207 | .reg_spm_apsrc_req_reserved_mask_b = 1, |
| 208 | /* [16] */ |
| 209 | .reg_spm_vrf18_req_reserved_mask_b = 1, |
| 210 | /* [17] */ |
| 211 | .reg_spm_ddr_en_reserved_mask_b = 1, |
| 212 | /* [18] */ |
| 213 | .reg_disp0_apsrc_req_mask_b = 1, |
| 214 | /* [19] */ |
| 215 | .reg_disp0_ddr_en_mask_b = 1, |
| 216 | /* [20] */ |
| 217 | .reg_disp1_apsrc_req_mask_b = 1, |
| 218 | /* [21] */ |
| 219 | .reg_disp1_ddr_en_mask_b = 1, |
| 220 | /* [22] */ |
| 221 | .reg_disp2_apsrc_req_mask_b = 1, |
| 222 | /* [23] */ |
| 223 | .reg_disp2_ddr_en_mask_b = 1, |
| 224 | /* [24] */ |
| 225 | .reg_disp3_apsrc_req_mask_b = 1, |
| 226 | /* [25] */ |
| 227 | .reg_disp3_ddr_en_mask_b = 1, |
| 228 | /* [26] */ |
| 229 | .reg_infrasys_apsrc_req_mask_b = 0, |
| 230 | /* [27] */ |
| 231 | .reg_infrasys_ddr_en_mask_b = 1, |
| 232 | |
| 233 | /* [28] */ |
| 234 | .reg_cg_check_srcclkena_mask_b = 1, |
| 235 | /* [29] */ |
| 236 | .reg_cg_check_apsrc_req_mask_b = 1, |
| 237 | /* [30] */ |
| 238 | .reg_cg_check_vrf18_req_mask_b = 1, |
| 239 | /* [31] */ |
| 240 | .reg_cg_check_ddr_en_mask_b = 1, |
| 241 | |
| 242 | /* SPM_SRC4_MASK */ |
| 243 | /* [8:0] */ |
| 244 | .reg_mcusys_merge_apsrc_req_mask_b = 0x17, |
| 245 | /* [17:9] */ |
| 246 | .reg_mcusys_merge_ddr_en_mask_b = 0x17, |
| 247 | /* [19:18] */ |
| 248 | .reg_dramc_md32_infra_req_mask_b = 0, |
| 249 | /* [21:20] */ |
| 250 | .reg_dramc_md32_vrf18_req_mask_b = 0, |
| 251 | /* [23:22] */ |
| 252 | .reg_dramc_md32_ddr_en_mask_b = 0, |
| 253 | /* [24] */ |
| 254 | .reg_dvfsrc_event_trigger_mask_b = 1, |
| 255 | |
| 256 | /* SPM_WAKEUP_EVENT_MASK2 */ |
| 257 | /* [3:0] */ |
| 258 | .reg_sc_sw2spm_wakeup_mask_b = 0, |
| 259 | /* [4] */ |
| 260 | .reg_sc_adsp2spm_wakeup_mask_b = 0, |
| 261 | /* [8:5] */ |
| 262 | .reg_sc_sspm2spm_wakeup_mask_b = 0, |
| 263 | /* [9] */ |
| 264 | .reg_sc_scp2spm_wakeup_mask_b = 0, |
| 265 | /* [10] */ |
| 266 | .reg_csyspwrup_ack_mask = 0, |
| 267 | /* [11] */ |
| 268 | .reg_csyspwrup_req_mask = 1, |
| 269 | |
| 270 | /* SPM_WAKEUP_EVENT_MASK */ |
| 271 | /* [31:0] */ |
| 272 | .reg_wakeup_event_mask = 0xC1382213, |
| 273 | |
| 274 | /* SPM_WAKEUP_EVENT_EXT_MASK */ |
| 275 | /* [31:0] */ |
| 276 | .reg_ext_wakeup_event_mask = 0xFFFFFFFF, |
| 277 | }; |
| 278 | |
Bo-Chen Chen | 9d638a9 | 2022-08-29 19:09:38 +0800 | [diff] [blame] | 279 | void spm_set_power_control(const struct pwr_ctrl *pwrctrl) |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 280 | { |
| 281 | /* Auto-gen Start */ |
| 282 | |
| 283 | /* SPM_AP_STANDBY_CON */ |
| 284 | write32(&mtk_spm->spm_ap_standby_con, |
| 285 | ((pwrctrl->reg_wfi_op & 0x1) << 0) | |
| 286 | ((pwrctrl->reg_wfi_type & 0x1) << 1) | |
| 287 | ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | |
| 288 | ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | |
| 289 | ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | |
| 290 | ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | |
| 291 | ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | |
| 292 | ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); |
| 293 | |
| 294 | /* SPM_SRC_REQ */ |
| 295 | write32(&mtk_spm->spm_src_req, |
| 296 | ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | |
| 297 | ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | |
| 298 | ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | |
| 299 | ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | |
| 300 | ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | |
| 301 | ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | |
| 302 | ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | |
| 303 | ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | |
| 304 | ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | |
| 305 | ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); |
| 306 | |
| 307 | /* SPM_SRC_MASK */ |
| 308 | write32(&mtk_spm->spm_src_mask, |
| 309 | ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) | |
| 310 | ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) | |
| 311 | ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) | |
| 312 | ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) | |
| 313 | ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) | |
| 314 | ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) | |
| 315 | ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) | |
| 316 | ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) | |
| 317 | ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) | |
| 318 | ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) | |
| 319 | ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) | |
| 320 | ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) | |
| 321 | ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) | |
| 322 | ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) | |
| 323 | ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) | |
| 324 | ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) | |
| 325 | ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) | |
| 326 | ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) | |
| 327 | ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) | |
| 328 | ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) | |
| 329 | ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) | |
| 330 | ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) | |
| 331 | ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) | |
| 332 | ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) | |
| 333 | ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) | |
| 334 | ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) | |
| 335 | ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) | |
| 336 | ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) | |
| 337 | ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) | |
| 338 | ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29)); |
| 339 | |
| 340 | /* SPM_SRC2_MASK */ |
| 341 | write32(&mtk_spm->spm_src2_mask, |
| 342 | ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) | |
| 343 | ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) | |
| 344 | ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) | |
| 345 | ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) | |
| 346 | ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) | |
| 347 | ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) | |
| 348 | ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) | |
| 349 | ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) | |
| 350 | ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) | |
| 351 | ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) | |
| 352 | ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) | |
| 353 | ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) | |
| 354 | ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) | |
| 355 | ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) | |
| 356 | ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) | |
| 357 | ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) | |
| 358 | ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) | |
| 359 | ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) | |
| 360 | ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) | |
| 361 | ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) | |
| 362 | ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) | |
| 363 | ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) | |
| 364 | ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) | |
| 365 | ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) | |
| 366 | ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) | |
| 367 | ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) | |
| 368 | ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) | |
| 369 | ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) | |
| 370 | ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) | |
| 371 | ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29)); |
| 372 | |
| 373 | /* SPM_SRC3_MASK */ |
| 374 | write32(&mtk_spm->spm_src3_mask, |
| 375 | ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) | |
| 376 | ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) | |
| 377 | ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) | |
| 378 | ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) | |
| 379 | ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) | |
| 380 | ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) | |
| 381 | ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) | |
| 382 | ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) | |
| 383 | ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) | |
| 384 | ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) | |
| 385 | ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) | |
| 386 | ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) | |
| 387 | ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) | |
| 388 | ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) | |
| 389 | ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) | |
| 390 | ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) | |
| 391 | ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) | |
| 392 | ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) | |
| 393 | ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) | |
| 394 | ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) | |
| 395 | ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) | |
| 396 | ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) | |
| 397 | ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) | |
| 398 | ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) | |
| 399 | ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) | |
| 400 | ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) | |
| 401 | ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) | |
| 402 | ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27)); |
| 403 | |
| 404 | /* SPM_SRC4_MASK */ |
| 405 | write32(&mtk_spm->spm_src4_mask, 0x1fc0000); |
| 406 | |
| 407 | /* SPM_WAKEUP_EVENT_MASK */ |
| 408 | write32(&mtk_spm->spm_wakeup_event_mask, |
| 409 | ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); |
| 410 | |
| 411 | /* SPM_WAKEUP_EVENT_EXT_MASK */ |
| 412 | write32(&mtk_spm->spm_wakeup_event_ext_mask, |
| 413 | ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); |
| 414 | |
| 415 | /* Auto-gen End */ |
| 416 | } |
| 417 | |
Bo-Chen Chen | 9d638a9 | 2022-08-29 19:09:38 +0800 | [diff] [blame] | 418 | void spm_register_init(void) |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 419 | { |
| 420 | /* Enable register control */ |
| 421 | write32(&mtk_spm->poweron_config_set, |
| 422 | SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); |
| 423 | |
| 424 | /* Init power control register */ |
| 425 | write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); |
| 426 | write32(&mtk_spm->pcm_pwr_io_en, 0); |
| 427 | |
| 428 | /* Reset PCM */ |
| 429 | write32(&mtk_spm->pcm_con0, |
| 430 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); |
| 431 | write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); |
| 432 | write32(&mtk_spm->pcm_con1, |
| 433 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB | |
| 434 | REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB | |
| 435 | REG_MD32_APB_INTERNAL_EN_LSB); |
| 436 | |
| 437 | /* Initial SPM CLK control register */ |
| 438 | SET32_BITFIELDS(&mtk_spm->spm_clk_con, |
| 439 | REG_SYSCLK1_SRC_MD2_SRCCLKENA, 1); |
| 440 | |
| 441 | /* Clean wakeup event raw status */ |
| 442 | write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); |
| 443 | |
| 444 | /* Clean ISR status */ |
| 445 | write32(&mtk_spm->spm_irq_mask, ISRM_ALL); |
| 446 | write32(&mtk_spm->spm_irq_sta, ISRC_ALL); |
| 447 | write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); |
| 448 | |
| 449 | /* Init r7 with POWER_ON_VAL1 */ |
| 450 | write32(&mtk_spm->pcm_reg_data_ini, |
| 451 | read32(&mtk_spm->spm_power_on_val1)); |
| 452 | write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); |
| 453 | write32(&mtk_spm->pcm_pwr_io_en, 0); |
| 454 | |
| 455 | /* Configure ARMPLL Control Mode for MCDI */ |
| 456 | write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF); |
| 457 | |
| 458 | /* Init for SPM Resource ACK */ |
| 459 | write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF); |
| 460 | write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF); |
| 461 | write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF); |
| 462 | write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF); |
| 463 | |
| 464 | /* Init VCORE DVFS Status */ |
| 465 | SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, |
| 466 | SPM_DVFS_FORCE_ENABLE_LSB, 0, |
| 467 | SPM_DVFSRC_ENABLE_LSB, 1); |
| 468 | write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF); |
| 469 | write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF); |
| 470 | |
| 471 | } |
| 472 | |
Bo-Chen Chen | 9d638a9 | 2022-08-29 19:09:38 +0800 | [diff] [blame] | 473 | void spm_reset_and_init_pcm(void) |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 474 | { |
| 475 | bool first_load_fw = true; |
| 476 | |
| 477 | /* Check the SPM FW is run or not */ |
| 478 | if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) & |
| 479 | MD32PCM_CFGREG_SW_RSTN_RUN) |
| 480 | first_load_fw = false; |
| 481 | |
| 482 | if (!first_load_fw) { |
| 483 | spm_code_swapping(); |
| 484 | /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */ |
| 485 | write32(&mtk_spm->spm_power_on_val0, |
| 486 | read32(&mtk_spm->pcm_reg0_data)); |
| 487 | } |
| 488 | |
| 489 | /* Disable r0 and r7 to control power */ |
| 490 | write32(&mtk_spm->pcm_pwr_io_en, 0); |
| 491 | |
| 492 | /* Disable pcm timer after leaving FW */ |
| 493 | clrsetbits32(&mtk_spm->pcm_con1, |
| 494 | RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); |
| 495 | |
| 496 | /* Reset PCM */ |
| 497 | write32(&mtk_spm->pcm_con0, |
| 498 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); |
| 499 | write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); |
| 500 | |
| 501 | /* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ |
| 502 | clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB, |
| 503 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB | |
| 504 | REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB | |
| 505 | REG_MD32_APB_INTERNAL_EN_LSB); |
| 506 | } |
| 507 | |
Bo-Chen Chen | 9d638a9 | 2022-08-29 19:09:38 +0800 | [diff] [blame] | 508 | void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 509 | { |
| 510 | u32 val, mask; |
| 511 | |
| 512 | /* Toggle event counter clear */ |
| 513 | setbits32(&mtk_spm->pcm_con1, |
| 514 | SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); |
| 515 | |
| 516 | /* Toggle for reset SYS TIMER start point */ |
| 517 | SET32_BITFIELDS(&mtk_spm->sys_timer_con, |
| 518 | SYS_TIMER_START_EN_LSB, 1); |
| 519 | |
| 520 | if (pwrctrl->timer_val_cust == 0) |
| 521 | val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; |
| 522 | else |
| 523 | val = pwrctrl->timer_val_cust; |
| 524 | |
| 525 | write32(&mtk_spm->pcm_timer_val, val); |
| 526 | |
| 527 | /* Disable pcm timer */ |
| 528 | clrsetbits32(&mtk_spm->pcm_con1, |
| 529 | RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); |
| 530 | |
| 531 | /* Unmask AP wakeup source */ |
| 532 | if (pwrctrl->wake_src_cust == 0) |
| 533 | mask = pwrctrl->wake_src; |
| 534 | else |
| 535 | mask = pwrctrl->wake_src_cust; |
| 536 | |
| 537 | write32(&mtk_spm->spm_wakeup_event_mask, ~mask); |
| 538 | |
| 539 | /* Unmask SPM ISR */ |
| 540 | SET32_BITFIELDS(&mtk_spm->spm_irq_mask, |
| 541 | ISRM_TWAM_BF, 1, |
| 542 | ISRM_RET_IRQ_AUX_BF, 0x3ff); |
| 543 | |
| 544 | /* Toggle event counter clear */ |
| 545 | clrsetbits32(&mtk_spm->pcm_con1, |
| 546 | SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY); |
| 547 | |
| 548 | /* Toggle for reset SYS TIMER start point */ |
| 549 | SET32_BITFIELDS(&mtk_spm->sys_timer_con, |
| 550 | SYS_TIMER_START_EN_LSB, 0); |
| 551 | } |
| 552 | |
Bo-Chen Chen | 9d638a9 | 2022-08-29 19:09:38 +0800 | [diff] [blame] | 553 | const struct pwr_ctrl *get_pwr_ctrl(void) |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 554 | { |
Bo-Chen Chen | 9d638a9 | 2022-08-29 19:09:38 +0800 | [diff] [blame] | 555 | return &spm_init_ctrl; |
Dawei Chien | dd8f241 | 2021-05-12 18:17:26 +0800 | [diff] [blame] | 556 | } |