Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 2 | |
Pratik Prajapati | 653f019 | 2017-08-28 15:15:38 -0700 | [diff] [blame] | 3 | #include <cpu/x86/msr.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 4 | #include <delay.h> |
| 5 | #include <device/device.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 7 | #include <intelblocks/power_limit.h> |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 8 | #include <intelblocks/systemagent.h> |
Sean Rhodes | 66c8062 | 2021-07-13 07:23:22 +0100 | [diff] [blame] | 9 | #include <option.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 10 | #include <soc/cpu.h> |
| 11 | #include <soc/iomap.h> |
Pratik Prajapati | 653f019 | 2017-08-28 15:15:38 -0700 | [diff] [blame] | 12 | #include <soc/msr.h> |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 13 | #include <soc/pci_devs.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 14 | #include <soc/systemagent.h> |
Sean Rhodes | 66c8062 | 2021-07-13 07:23:22 +0100 | [diff] [blame] | 15 | #include <types.h> |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 16 | #include "chip.h" |
| 17 | |
Sean Rhodes | 66c8062 | 2021-07-13 07:23:22 +0100 | [diff] [blame] | 18 | bool soc_vtd_enabled(void) |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 19 | { |
Sean Rhodes | 66c8062 | 2021-07-13 07:23:22 +0100 | [diff] [blame] | 20 | const unsigned int vtd = get_uint_option("vtd", 1); |
| 21 | if (!vtd) |
| 22 | return false; |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 23 | struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 24 | return root_dev && |
| 25 | !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); |
| 26 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 27 | |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 28 | /* |
| 29 | * SoC implementation |
| 30 | * |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 31 | * Add all known fixed memory ranges for Host Controller/Memory |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 32 | * controller. |
| 33 | */ |
| 34 | void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 35 | { |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 36 | static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 37 | { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 38 | "PCIEXBAR" }, |
| 39 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 40 | { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, |
| 41 | { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, |
| 42 | { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" }, |
| 43 | { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, |
| 44 | }; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 45 | |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 46 | sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| 47 | ARRAY_SIZE(soc_fixed_resources)); |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 48 | |
Sean Rhodes | 66c8062 | 2021-07-13 07:23:22 +0100 | [diff] [blame] | 49 | if (soc_vtd_enabled()) { |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 50 | if (is_devfn_enabled(SA_DEVFN_IGD)) |
Maxim Polyakov | 5806665 | 2019-04-25 12:32:15 +0300 | [diff] [blame] | 51 | sa_add_fixed_mmio_resources(dev, index, |
| 52 | &soc_gfxvt_mmio_descriptor, 1); |
| 53 | |
| 54 | sa_add_fixed_mmio_resources(dev, index, |
| 55 | &soc_vtvc0_mmio_descriptor, 1); |
| 56 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 57 | } |
| 58 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 59 | /* |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 60 | * SoC implementation |
| 61 | * |
| 62 | * Perform System Agent Initialization during Ramstage phase. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 63 | */ |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 64 | void soc_systemagent_init(struct device *dev) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 65 | { |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 66 | struct soc_power_limits_config *soc_config; |
| 67 | config_t *config; |
| 68 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 69 | /* Enable Power Aware Interrupt Routing */ |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 70 | enable_power_aware_intr(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 71 | |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 72 | /* Enable BIOS Reset CPL */ |
| 73 | enable_bios_reset_cpl(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 74 | |
| 75 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 76 | mdelay(1); |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 77 | config = config_of_soc(); |
| 78 | soc_config = &config->power_limits_config; |
| 79 | set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 80 | } |
Pratik Prajapati | 653f019 | 2017-08-28 15:15:38 -0700 | [diff] [blame] | 81 | |
| 82 | int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, |
| 83 | uint64_t *prmrr_mask) |
| 84 | { |
| 85 | msr_t msr; |
Pratik Prajapati | 6a051f2 | 2017-08-28 15:30:20 -0700 | [diff] [blame] | 86 | msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE); |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 87 | *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo; |
Pratik Prajapati | 6a051f2 | 2017-08-28 15:30:20 -0700 | [diff] [blame] | 88 | msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK); |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 89 | *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo; |
Pratik Prajapati | 653f019 | 2017-08-28 15:15:38 -0700 | [diff] [blame] | 90 | return 0; |
| 91 | } |
Patrick Rudolph | bf72dcb | 2020-05-12 16:04:47 +0200 | [diff] [blame] | 92 | |
| 93 | uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) |
| 94 | { |
| 95 | switch (capid0_a_ddrsz) { |
| 96 | case 1: |
| 97 | return 8192; |
| 98 | case 2: |
| 99 | return 4096; |
| 100 | case 3: |
| 101 | return 2048; |
| 102 | default: |
| 103 | return 32768; |
| 104 | } |
| 105 | } |