Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <intelblocks/p2sb.h> |
Elyes Haouas | d1bf9bf | 2022-10-31 12:27:23 +0100 | [diff] [blame] | 5 | #include <types.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 6 | |
| 7 | void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) |
| 8 | { |
| 9 | uint32_t mask; |
| 10 | |
| 11 | if (count != P2SB_EP_MASK_MAX_REG) { |
| 12 | printk(BIOS_ERR, "Unable to program EPMASK registers\n"); |
| 13 | return; |
| 14 | } |
| 15 | |
| 16 | /* |
| 17 | * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband |
| 18 | * access for PCI Root Bridge. |
| 19 | * Set p2sb PCI offset EPMASK5 [17, 16,10, 1] to disable Sideband |
| 20 | * access for MIPI controller. |
| 21 | */ |
| 22 | mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | |
| 23 | (1 << 16) | (1 << 10) | (1 << 1); |
| 24 | |
| 25 | ep_mask[P2SB_EP_MASK_5_REG] = mask; |
| 26 | |
| 27 | /* |
| 28 | * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband |
| 29 | * access for XHCI controller. |
| 30 | */ |
| 31 | mask = (1 << 6) | (1 << 5); |
| 32 | |
| 33 | ep_mask[P2SB_EP_MASK_7_REG] = mask; |
| 34 | } |