Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 2 | |
Dinesh Gehlot | d83cd8b | 2023-01-17 05:15:55 +0000 | [diff] [blame] | 3 | #include <gpio.h> |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 4 | #include <intelblocks/pcr.h> |
| 5 | #include <soc/pcr.h> |
| 6 | #include <soc/pm.h> |
| 7 | |
| 8 | static const struct reset_mapping rst_map[] = { |
| 9 | { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, |
| 10 | { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, |
| 11 | { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, |
| 12 | /* (applicable only for GPD group) */ |
| 13 | { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, |
| 14 | }; |
| 15 | |
| 16 | static const struct pad_group dnv_community_nc_groups[] = { |
| 17 | INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ3_N), |
| 18 | INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ4_N, NORTH_ALL_MEMHOT_N), |
| 19 | }; |
| 20 | |
| 21 | static const struct pad_group dnv_community_sc_dfx_groups[] = { |
| 22 | INTEL_GPP(SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT15), |
| 23 | }; |
| 24 | |
| 25 | static const struct pad_group dnv_community_sc0_groups[] = { |
| 26 | INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA0_LED_N), |
| 27 | INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA1_LED_N, SOUTH_GROUP0_DFX_SPARE4), |
| 28 | }; |
| 29 | |
| 30 | static const struct pad_group dnv_community_sc1_groups[] = { |
| 31 | INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_STROBE), |
| 32 | INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_CLK, SOUTH_GROUP1_GPIO_3), |
| 33 | }; |
| 34 | |
| 35 | static const struct pad_community dnv_gpio_communities[] = { |
| 36 | { |
| 37 | .port = PID_GPIOCOM1, |
| 38 | .first_pad = SOUTH_GROUP1_SUSPWRDNACK, |
| 39 | .last_pad = SOUTH_GROUP1_GPIO_3, |
| 40 | .num_gpi_regs = NUM_SC1_GPI_REGS, |
| 41 | .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS + |
| 42 | NUM_SC0_GPI_REGS, |
| 43 | .pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET, |
| 44 | .host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN, |
Karthikeyan Ramasubramanian | c126084 | 2019-04-23 15:18:51 -0600 | [diff] [blame] | 45 | .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IS, |
| 46 | .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IE, |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 47 | .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS, |
| 48 | .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN, |
| 49 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 50 | .name = "GPIO_GPE_SC1", |
| 51 | .acpi_path = "\\_SB.GPO3", |
| 52 | .reset_map = rst_map, |
| 53 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 54 | .groups = dnv_community_sc1_groups, |
| 55 | .num_groups = ARRAY_SIZE(dnv_community_sc1_groups), |
| 56 | }, { |
| 57 | .port = PID_GPIOCOM1, |
| 58 | .first_pad = SOUTH_GROUP0_SMB3_CLTT_DATA, |
| 59 | .last_pad = SOUTH_GROUP0_DFX_SPARE4, |
| 60 | .num_gpi_regs = NUM_SC0_GPI_REGS, |
| 61 | .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS, |
| 62 | .pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET, |
| 63 | .host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN, |
Karthikeyan Ramasubramanian | c126084 | 2019-04-23 15:18:51 -0600 | [diff] [blame] | 64 | .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IS, |
| 65 | .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IE, |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 66 | .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS, |
| 67 | .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN, |
| 68 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 69 | .name = "GPIO_GPE_SC0", |
| 70 | .acpi_path = "\\_SB.GPO2", |
| 71 | .reset_map = rst_map, |
| 72 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 73 | .groups = dnv_community_sc0_groups, |
| 74 | .num_groups = ARRAY_SIZE(dnv_community_sc0_groups), |
| 75 | }, { |
| 76 | .port = PID_GPIOCOM1, |
| 77 | .first_pad = SOUTH_DFX_DFX_PORT_CLK0, |
| 78 | .last_pad = SOUTH_DFX_DFX_PORT15, |
| 79 | .num_gpi_regs = NUM_SC_DFX_GPI_REGS, |
| 80 | .gpi_status_offset = NUM_NC_GPI_REGS, |
| 81 | .pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET, |
| 82 | .host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN, |
Karthikeyan Ramasubramanian | c126084 | 2019-04-23 15:18:51 -0600 | [diff] [blame] | 83 | .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IS, |
| 84 | .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IE, |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 85 | .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS, |
| 86 | .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN, |
| 87 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 88 | .name = "GPIO_GPE_SC_DFX", |
| 89 | .acpi_path = "\\_SB.GPO1", |
| 90 | .reset_map = rst_map, |
| 91 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 92 | .groups = dnv_community_sc_dfx_groups, |
| 93 | .num_groups = ARRAY_SIZE(dnv_community_sc_dfx_groups), |
| 94 | }, { |
| 95 | .port = PID_GPIOCOM0, |
| 96 | .first_pad = NORTH_ALL_GBE0_SDP0, |
| 97 | .last_pad = NORTH_ALL_MEMHOT_N, |
| 98 | .num_gpi_regs = NUM_NC_GPI_REGS, |
| 99 | .gpi_status_offset = 0, |
| 100 | .pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET, |
| 101 | .host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN, |
Karthikeyan Ramasubramanian | c126084 | 2019-04-23 15:18:51 -0600 | [diff] [blame] | 102 | .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IS, |
| 103 | .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IE, |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 104 | .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS, |
| 105 | .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN, |
| 106 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 107 | .name = "GPIO_GPE_NC", |
| 108 | .acpi_path = "\\_SB.GPO0", |
| 109 | .reset_map = rst_map, |
| 110 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 111 | .groups = dnv_community_nc_groups, |
| 112 | .num_groups = ARRAY_SIZE(dnv_community_nc_groups), |
| 113 | } |
| 114 | }; |
| 115 | |
| 116 | const struct pad_community *soc_gpio_get_community(size_t *num_communities) |
| 117 | { |
| 118 | *num_communities = ARRAY_SIZE(dnv_gpio_communities); |
| 119 | return dnv_gpio_communities; |
| 120 | } |