Angel Pons | c3f58f6 | 2020-04-05 15:46:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
| 4 | #include <acpi/acpigen.h> |
Angel Pons | e0e2890 | 2020-08-03 13:26:21 +0200 | [diff] [blame] | 5 | #include <arch/ioapic.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 7 | #include <arch/smp/mpspec.h> |
| 8 | #include <console/console.h> |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 9 | #include <types.h> |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 10 | #include <cpu/x86/msr.h> |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 11 | #include <cpu/intel/turbo.h> |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 12 | |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 13 | #include <soc/iomap.h> |
| 14 | #include <soc/irq.h> |
| 15 | #include <soc/msr.h> |
| 16 | #include <soc/pattrs.h> |
Angel Pons | b5320b2 | 2020-07-07 18:27:30 +0200 | [diff] [blame] | 17 | #include <soc/pm.h> |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 18 | |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 19 | #define MWAIT_RES(state, sub_state) \ |
| 20 | { \ |
| 21 | .addrl = (((state) << 4) | (sub_state)), \ |
| 22 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 23 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 24 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 25 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 26 | } |
| 27 | |
| 28 | /* C-state map without S0ix */ |
Angel Pons | d2794ce | 2021-10-17 12:59:43 +0200 | [diff] [blame] | 29 | static const acpi_cstate_t cstate_map[] = { |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 30 | { |
| 31 | /* C1 */ |
| 32 | .ctype = 1, /* ACPI C1 */ |
| 33 | .latency = 1, |
| 34 | .power = 1000, |
| 35 | .resource = MWAIT_RES(0, 0), |
| 36 | }, |
| 37 | { |
| 38 | /* C6NS with no L2 shrink */ |
| 39 | /* NOTE: this substate is above CPUID limit */ |
| 40 | .ctype = 2, /* ACPI C2 */ |
| 41 | .latency = 500, |
| 42 | .power = 10, |
Duncan Laurie | 22f1dcd | 2013-12-02 10:14:47 -0800 | [diff] [blame] | 43 | .resource = MWAIT_RES(5, 1), |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 44 | }, |
| 45 | { |
| 46 | /* C6FS with full L2 shrink */ |
| 47 | .ctype = 3, /* ACPI C3 */ |
| 48 | .latency = 1500, /* 1.5ms worst case */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 49 | .power = 1, |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 50 | .resource = MWAIT_RES(5, 2), |
| 51 | } |
| 52 | }; |
| 53 | |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 54 | static u8 soc_madt_sci_irq_polarity(u8 sci_irq) |
| 55 | { |
| 56 | if (sci_irq >= 20) |
| 57 | return MP_IRQ_POLARITY_LOW; |
| 58 | else |
| 59 | return MP_IRQ_POLARITY_HIGH; |
| 60 | } |
| 61 | |
| 62 | #define ACPI_SCI_IRQ 9 |
| 63 | |
| 64 | void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 65 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 66 | u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 67 | int sci_irq = ACPI_SCI_IRQ; |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 68 | int scis; |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 69 | |
| 70 | /* Determine how SCI is routed. */ |
| 71 | scis = read32(actl) & SCIS_MASK; |
| 72 | switch (scis) { |
| 73 | case SCIS_IRQ9: |
| 74 | case SCIS_IRQ10: |
| 75 | case SCIS_IRQ11: |
| 76 | sci_irq = scis - SCIS_IRQ9 + 9; |
| 77 | break; |
| 78 | case SCIS_IRQ20: |
| 79 | case SCIS_IRQ21: |
| 80 | case SCIS_IRQ22: |
| 81 | case SCIS_IRQ23: |
| 82 | sci_irq = scis - SCIS_IRQ20 + 20; |
| 83 | break; |
| 84 | default: |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 85 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 86 | break; |
| 87 | } |
| 88 | |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 89 | *gsi = sci_irq; |
| 90 | *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; |
| 91 | *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); |
| 92 | |
| 93 | printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 94 | } |
| 95 | |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 96 | static acpi_tstate_t soc_tss_table[] = { |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 97 | { 100, 1000, 0, 0x00, 0 }, |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 98 | { 88, 875, 0, 0x1e, 0 }, |
| 99 | { 75, 750, 0, 0x1c, 0 }, |
| 100 | { 63, 625, 0, 0x1a, 0 }, |
| 101 | { 50, 500, 0, 0x18, 0 }, |
| 102 | { 38, 375, 0, 0x16, 0 }, |
| 103 | { 25, 250, 0, 0x14, 0 }, |
| 104 | { 13, 125, 0, 0x12, 0 }, |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 105 | }; |
| 106 | |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 107 | static void generate_t_state_entries(int core, int cores_per_package) |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 108 | { |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 109 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 110 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 111 | |
| 112 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 113 | acpigen_write_empty_PTC(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 114 | |
| 115 | /* Set NVS controlled T-state limit */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 116 | acpigen_write_TPC("\\TLVL"); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 117 | |
| 118 | /* Write TSS table for MSR access */ |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 119 | acpigen_write_TSS_package(ARRAY_SIZE(soc_tss_table), soc_tss_table); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 123 | { |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 124 | u32 m, power; |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 125 | |
| 126 | /* |
| 127 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 128 | */ |
| 129 | |
| 130 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 131 | m = (m * m) / 1000; |
| 132 | |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 133 | /* |
| 134 | * Power = (ratio / p1_ratio) * m * TDP |
| 135 | */ |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 136 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 137 | power *= (m / 100) * (tdp / 1000); |
| 138 | power /= 1000; |
| 139 | |
| 140 | return (int)power; |
| 141 | } |
| 142 | |
Kyösti Mälkki | d521b96 | 2023-04-12 21:44:49 +0300 | [diff] [blame] | 143 | static void generate_p_state_entries(int core) |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 144 | { |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 145 | int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; |
| 146 | int coord_type, power_max, power_unit, num_entries; |
| 147 | int ratio, power, clock, clock_max; |
| 148 | int vid, vid_turbo, vid_min, vid_max, vid_range_2; |
| 149 | u32 control_status; |
| 150 | const struct pattrs *pattrs = pattrs_get(); |
| 151 | msr_t msr; |
| 152 | |
| 153 | /* Inputs from CPU attributes */ |
| 154 | ratio_max = pattrs->iacore_ratios[IACORE_MAX]; |
| 155 | ratio_min = pattrs->iacore_ratios[IACORE_LFM]; |
| 156 | vid_max = pattrs->iacore_vids[IACORE_MAX]; |
| 157 | vid_min = pattrs->iacore_vids[IACORE_LFM]; |
| 158 | |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 159 | /* Set P-states coordination type based on MSR disable bit */ |
Duncan Laurie | 31ac9e3 | 2014-03-28 10:52:13 -0700 | [diff] [blame] | 160 | coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL; |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 161 | |
| 162 | /* Max Non-Turbo Frequency */ |
| 163 | clock_max = (ratio_max * pattrs->bclk_khz) / 1000; |
| 164 | |
| 165 | /* Calculate CPU TDP in mW */ |
| 166 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 167 | power_unit = 1 << (msr.lo & 0xf); |
| 168 | msr = rdmsr(MSR_PKG_POWER_LIMIT); |
| 169 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 170 | |
| 171 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 172 | acpigen_write_empty_PCT(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 173 | |
Duncan Laurie | ad8d913 | 2013-12-10 07:41:33 -0800 | [diff] [blame] | 174 | /* Write _PPC with NVS specified limit on supported P-state */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 175 | acpigen_write_PPC_NVS(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 176 | |
| 177 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 178 | acpigen_write_PSD_package(core, 1, coord_type); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 179 | |
| 180 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 181 | acpigen_write_name("_PSS"); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 182 | |
| 183 | /* Determine ratio points */ |
| 184 | ratio_step = 1; |
| 185 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 186 | while (num_entries > 15) { /* ACPI max is 15 ratios */ |
| 187 | ratio_step <<= 1; |
| 188 | num_entries >>= 1; |
| 189 | } |
| 190 | |
| 191 | /* P[T] is Turbo state if enabled */ |
| 192 | if (get_turbo_state() == TURBO_ENABLED) { |
| 193 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 194 | acpigen_write_package(num_entries + 2); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 195 | |
| 196 | ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; |
| 197 | vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; |
| 198 | control_status = (ratio_turbo << 8) | vid_turbo; |
| 199 | |
| 200 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 201 | acpigen_write_PSS_package( |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 202 | clock_max + 1, /* MHz */ |
| 203 | power_max, /* mW */ |
| 204 | 10, /* lat1 */ |
| 205 | 10, /* lat2 */ |
| 206 | control_status, /* control */ |
| 207 | control_status); /* status */ |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 208 | } else { |
| 209 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 210 | acpigen_write_package(num_entries + 1); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 211 | ratio_turbo = ratio_max; |
| 212 | vid_turbo = vid_max; |
| 213 | } |
| 214 | |
| 215 | /* First regular entry is max non-turbo ratio */ |
| 216 | control_status = (ratio_max << 8) | vid_max; |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 217 | acpigen_write_PSS_package( |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 218 | clock_max, /* MHz */ |
| 219 | power_max, /* mW */ |
| 220 | 10, /* lat1 */ |
| 221 | 10, /* lat2 */ |
| 222 | control_status, /* control */ |
| 223 | control_status); /* status */ |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 224 | |
| 225 | /* Set up ratio and vid ranges for VID calculation */ |
| 226 | ratio_range_2 = (ratio_turbo - ratio_min) * 2; |
| 227 | vid_range_2 = (vid_turbo - vid_min) * 2; |
| 228 | |
| 229 | /* Generate the remaining entries */ |
| 230 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 231 | ratio >= ratio_min; ratio -= ratio_step) { |
| 232 | |
| 233 | /* Calculate VID for this ratio */ |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 234 | vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min; |
| 235 | |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 236 | /* Round up if remainder */ |
| 237 | if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) |
| 238 | vid++; |
| 239 | |
| 240 | /* Calculate power at this ratio */ |
| 241 | power = calculate_power(power_max, ratio_max, ratio); |
| 242 | clock = (ratio * pattrs->bclk_khz) / 1000; |
| 243 | control_status = (ratio << 8) | (vid & 0xff); |
| 244 | |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 245 | acpigen_write_PSS_package( |
Angel Pons | 06e44a8 | 2020-07-07 17:34:21 +0200 | [diff] [blame] | 246 | clock, /* MHz */ |
| 247 | power, /* mW */ |
| 248 | 10, /* lat1 */ |
| 249 | 10, /* lat2 */ |
| 250 | control_status, /* control */ |
| 251 | control_status); /* status */ |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | /* Fix package length */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 255 | acpigen_pop_len(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 256 | } |
| 257 | |
Kyösti Mälkki | d521b96 | 2023-04-12 21:44:49 +0300 | [diff] [blame] | 258 | static void generate_cpu_entry(int core, int cores_per_package) |
| 259 | { |
| 260 | /* Generate Scope(\_SB) { Device(CPUx */ |
| 261 | acpigen_write_processor_device(core); |
| 262 | |
| 263 | /* Generate P-state tables */ |
| 264 | generate_p_state_entries(core); |
| 265 | |
| 266 | /* Generate C-state tables */ |
| 267 | acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map)); |
| 268 | |
| 269 | /* Generate T-state tables */ |
| 270 | generate_t_state_entries(core, cores_per_package); |
| 271 | |
| 272 | acpigen_write_processor_device_end(); |
| 273 | } |
| 274 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 275 | void generate_cpu_entries(const struct device *device) |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 276 | { |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 277 | int core; |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 278 | const struct pattrs *pattrs = pattrs_get(); |
| 279 | |
Kyösti Mälkki | d521b96 | 2023-04-12 21:44:49 +0300 | [diff] [blame] | 280 | for (core = 0; core < pattrs->num_cpus; core++) |
| 281 | generate_cpu_entry(core, pattrs->num_cpus); |
Arthur Heymans | a783305 | 2018-11-28 12:20:14 +0100 | [diff] [blame] | 282 | |
| 283 | /* PPKG is usually used for thermal management |
| 284 | of the first and only package. */ |
| 285 | acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus); |
| 286 | |
| 287 | /* Add a method to notify processor nodes */ |
| 288 | acpigen_write_processor_cnot(pattrs->num_cpus); |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 289 | } |