Joseph Smith | b94a79f | 2010-06-21 23:25:06 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; either version 2 of the License, or |
| 9 | ## (at your option) any later version. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
| 16 | ## You should have received a copy of the GNU General Public License |
| 17 | ## along with this program; if not, write to the Free Software |
| 18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | ## |
| 20 | |
| 21 | chip northbridge/intel/i82810 # Northbridge |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame^] | 22 | device cpu_cluster 0 on # APIC cluster |
Joseph Smith | b94a79f | 2010-06-21 23:25:06 +0000 | [diff] [blame] | 23 | chip cpu/intel/socket_FC_PGA370 # CPU |
| 24 | device lapic 0 on end # APIC |
| 25 | end |
| 26 | end |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 27 | device domain 0 on # PCI domain |
Joseph Smith | b94a79f | 2010-06-21 23:25:06 +0000 | [diff] [blame] | 28 | device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) |
| 29 | device pci 1.0 on end # Chipset Graphics Controller (CGC) |
| 30 | chip southbridge/intel/i82801bx # Southbridge |
| 31 | register "pirqa_routing" = "0x05" |
| 32 | register "pirqb_routing" = "0x06" |
| 33 | register "pirqc_routing" = "0x07" |
| 34 | register "pirqd_routing" = "0x09" |
| 35 | register "pirqe_routing" = "0x0a" |
| 36 | register "pirqf_routing" = "0x80" |
| 37 | register "pirqg_routing" = "0x80" |
| 38 | register "pirqh_routing" = "0x0b" |
| 39 | |
| 40 | register "ide0_enable" = "1" |
| 41 | register "ide1_enable" = "1" |
| 42 | |
| 43 | device pci 1e.0 on end # PCI bridge |
| 44 | device pci 1f.0 on # ISA bridge |
| 45 | chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102) |
| 46 | device pnp 4e.0 on # Floppy |
| 47 | io 0x60 = 0x3f0 |
| 48 | irq 0x70 = 6 |
| 49 | drq 0x74 = 2 |
| 50 | end |
| 51 | device pnp 4e.3 on # Parallel port |
| 52 | io 0x60 = 0x378 |
| 53 | irq 0x70 = 7 |
| 54 | drq 0x74 = 4 |
| 55 | end |
| 56 | device pnp 4e.4 on # COM1 |
| 57 | io 0x60 = 0x3f8 |
| 58 | irq 0x70 = 4 |
| 59 | end |
| 60 | device pnp 4e.5 off end # COM2 |
| 61 | device pnp 4e.7 on # PS/2 keyboard / mouse |
| 62 | io 0x60 = 0x60 |
| 63 | io 0x62 = 0x64 |
| 64 | irq 0x70 = 1 # PS/2 keyboard interrupt |
| 65 | irq 0x72 = 12 # PS/2 mouse interrupt |
| 66 | end |
| 67 | device pnp 4e.9 off end # Game port |
| 68 | device pnp 4e.a on # Runtime registers |
| 69 | io 0x60 = 0x800 |
| 70 | end |
| 71 | device pnp 4e.b off end # MPU-401 |
| 72 | end |
| 73 | end |
| 74 | device pci 1f.1 on end # IDE |
| 75 | device pci 1f.2 on end # USB |
| 76 | device pci 1f.3 on end # SMbus |
| 77 | device pci 1f.4 on end # USB |
| 78 | device pci 1f.5 on end # Audio controller |
| 79 | device pci 1f.6 off end # Modem controller |
| 80 | end |
| 81 | end |
| 82 | end |