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Ricardo Martins892d8d22012-08-06 05:40:07 +01001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
5##
6## This program is free software; you can redistribute it and/or
7## modify it under the terms of the GNU General Public License as
8## published by the Free Software Foundation; version 2 of
9## the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19## MA 02110-1301 USA
20##
21
22chip northbridge/amd/lx
Stefan Reinauer4aff4452013-02-12 14:17:15 -080023 device domain 0 on
Ricardo Martins892d8d22012-08-06 05:40:07 +010024 device pci 1.0 on end # Northbridge
25 device pci 1.1 on end # Video Adapter
26 device pci 1.2 on end # AES Security Block
27 chip southbridge/amd/cs5536
28 register "lpc_serirq_enable" = "0x000010da"
29 register "lpc_serirq_polarity" = "0x0000ef25"
30 register "lpc_serirq_mode" = "1"
31 register "enable_gpio_int_route" = "0x0d0c0700"
32 register "enable_ide_nand_flash" = "0"
33 register "enable_USBP4_device" = "0" # 0:host, 1:device
34 register "enable_USBP4_overcurrent" = "0"
35 register "com1_enable" = "0"
36 register "com2_enable" = "0"
37 register "unwanted_vpci[0]" = "0" # End of list has a zero
38 device pci 11.0 on end # IT8888
39 device pci e.0 on end # RTL8100C
40 device pci f.0 on # ISA Bridge
41 chip superio/smsc/smscsuperio # SMSC SCH3114
42 device pnp 2e.0 on # Floppy
43 io 0x60 = 0x3f0
44 irq 0x70 = 6
45 drq 0x74 = 2
46 end
47
48 device pnp 2e.3 on # Parallel port
49 io 0x60 = 0x378
50 irq 0x70 = 7
51 end
52
53 device pnp 2e.4 on # COM1
54 io 0x60 = 0x3f8
55 irq 0x70 = 4
56 end
57
58 device pnp 2e.5 on # COM2
59 io 0x60 = 0x2f8
60 irq 0x70 = 3
61 end
62
63 device pnp 2e.7 on # PS/2 keyboard/mouse
64 io 0x60 = 0x60
65 io 0x62 = 0x64
66 irq 0x70 = 1 # Keyboard
67 irq 0x72 = 12 # Mouse
68 end
69
70 device pnp 2e.a on # Runtime Register
71 io 0x60 = 0x400
72 end
73 end
74 end
75 device pci f.2 on end # IDE Controller
76 device pci f.3 on end # Audio
77 device pci f.4 on end # OHCI
78 device pci f.5 on end # EHCI
79 end
80 end
81 # APIC cluster is late CPU init.
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080082 device cpu_cluster 0 on
Ricardo Martins892d8d22012-08-06 05:40:07 +010083 chip cpu/amd/geode_lx
84 device lapic 0 on end
85 end
86 end
87end