Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <bootblock_common.h> |
Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 4 | #include <northbridge/intel/sandybridge/raminit.h> |
| 5 | #include <northbridge/intel/sandybridge/pei_data.h> |
| 6 | #include <southbridge/intel/bd82x6x/pch.h> |
| 7 | |
| 8 | #include <superio/nuvoton/common/nuvoton.h> |
| 9 | #include <superio/nuvoton/nct6779d/nct6779d.h> |
| 10 | |
| 11 | #include <option.h> |
| 12 | |
| 13 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) |
| 14 | |
| 15 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 16 | /* {enable, current, oc_pin} */ |
Keith Hui | 0aa069f | 2024-05-31 23:19:40 -0400 | [diff] [blame^] | 17 | {1, 8, 0}, /* Port 0: USB3 front internal header, top */ |
| 18 | {1, 8, 0}, /* Port 1: USB3 front internal header, bottom */ |
Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 19 | {1, 2, 1}, /* Port 2: USB3 rear, top */ |
| 20 | {1, 2, 1}, /* Port 3: USB3 rear, bottom */ |
| 21 | {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ |
| 22 | {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ |
| 23 | {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ |
| 24 | {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ |
Keith Hui | 0aa069f | 2024-05-31 23:19:40 -0400 | [diff] [blame^] | 25 | {1, 9, 4}, /* Port 8: USB2 internal header USB910, top */ |
| 26 | {1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */ |
Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 27 | {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ |
| 28 | {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ |
| 29 | {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ |
| 30 | {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ |
| 31 | }; |
| 32 | |
| 33 | void bootblock_mainboard_early_init(void) |
| 34 | { |
| 35 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 36 | |
| 37 | /* |
| 38 | * TODO: Put PCIe root port 7 (00:1c.6) into subtractive decode and have it accept I/O |
| 39 | * cycles. This should allow a POST card in the PCI slot, connected via an ASM1083 |
| 40 | * bridge to this port, to receive POST codes. |
| 41 | */ |
| 42 | } |
| 43 | |
Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 44 | void mainboard_fill_pei_data(struct pei_data *pei) |
| 45 | { |
Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 46 | /* |
| 47 | * USB 3 mode settings. |
| 48 | * These are obtained from option table then bit masked to keep within range. |
| 49 | */ |
| 50 | /* |
| 51 | * 0 = Disable: work always as USB 2.0(ehci) |
| 52 | * 1 = Enable: work always as USB 3.0(xhci) |
| 53 | * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver |
| 54 | * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver |
| 55 | * and reboots, it will keep the USB3.0 speed |
| 56 | */ |
| 57 | pei->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3; |
| 58 | /* 1=Load xHCI pre-OS drv */ |
| 59 | pei->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1; |
| 60 | /* |
| 61 | * 0=Don't use xHCI streams for better compatibility |
| 62 | * 1=use xHCI streams for better speed |
| 63 | */ |
| 64 | pei->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1; |
| 65 | } |