Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Elyes HAOUAS | 92f46aa | 2020-09-15 08:42:17 +0200 | [diff] [blame] | 3 | #include <arch/io.h> |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 4 | #include <bootblock_common.h> |
| 5 | #include <build.h> |
| 6 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 8 | #include <pc80/mc146818rtc.h> |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 9 | #include <soc/gpio.h> |
| 10 | #include <soc/iomap.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 11 | #include <soc/iosf.h> |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 12 | #include <soc/lpc.h> |
Kyösti Mälkki | 44f1af2 | 2019-11-06 08:56:18 +0200 | [diff] [blame] | 13 | #include <soc/msr.h> |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 14 | #include <soc/pm.h> |
| 15 | #include <soc/spi.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 16 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 17 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | { |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 19 | /* Call lib/bootblock.c main */ |
Kyösti Mälkki | 101ef0b | 2019-08-18 06:58:42 +0300 | [diff] [blame] | 20 | bootblock_main_with_basetime(base_timestamp); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | } |
| 22 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 23 | static void program_base_addresses(void) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 24 | { |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 25 | uint32_t reg; |
| 26 | const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 27 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 28 | /* Memory Mapped IO registers. */ |
| 29 | reg = PMC_BASE_ADDRESS | 2; |
| 30 | pci_write_config32(lpc_dev, PBASE, reg); |
| 31 | reg = IO_BASE_ADDRESS | 2; |
| 32 | pci_write_config32(lpc_dev, IOBASE, reg); |
| 33 | reg = ILB_BASE_ADDRESS | 2; |
| 34 | pci_write_config32(lpc_dev, IBASE, reg); |
| 35 | reg = SPI_BASE_ADDRESS | 2; |
| 36 | pci_write_config32(lpc_dev, SBASE, reg); |
| 37 | reg = MPHY_BASE_ADDRESS | 2; |
| 38 | pci_write_config32(lpc_dev, MPBASE, reg); |
| 39 | reg = PUNIT_BASE_ADDRESS | 2; |
| 40 | pci_write_config32(lpc_dev, PUBASE, reg); |
| 41 | reg = RCBA_BASE_ADDRESS | 1; |
| 42 | pci_write_config32(lpc_dev, RCBA, reg); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 43 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 44 | /* IO Port Registers. */ |
| 45 | reg = ACPI_BASE_ADDRESS | 2; |
| 46 | pci_write_config32(lpc_dev, ABASE, reg); |
| 47 | reg = GPIO_BASE_ADDRESS | 2; |
| 48 | pci_write_config32(lpc_dev, GBASE, reg); |
| 49 | } |
| 50 | |
| 51 | static void tco_disable(void) |
| 52 | { |
| 53 | uint32_t reg; |
| 54 | |
| 55 | reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); |
| 56 | reg |= TCO_TMR_HALT; |
| 57 | outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); |
| 58 | } |
| 59 | |
| 60 | static void spi_init(void) |
| 61 | { |
| 62 | void *scs = (void *)(SPI_BASE_ADDRESS + SCS); |
| 63 | void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); |
| 64 | uint32_t reg; |
| 65 | |
| 66 | /* Disable generating SMI when setting WPD bit. */ |
| 67 | write32(scs, read32(scs) & ~SMIWPEN); |
| 68 | /* |
| 69 | * Enable caching and prefetching in the SPI controller. Disable |
| 70 | * the SMM-only BIOS write and set WPD bit. |
| 71 | */ |
| 72 | reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; |
| 73 | reg &= ~EISS; |
| 74 | write32(bcr, reg); |
| 75 | } |
| 76 | |
| 77 | static void soc_rtc_init(void) |
| 78 | { |
| 79 | int rtc_failed = rtc_failure(); |
| 80 | |
| 81 | if (rtc_failed) { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 82 | printk(BIOS_ERR, "RTC Failure detected. Resetting date to %x/%x/%x%x\n", |
| 83 | COREBOOT_BUILD_MONTH_BCD, COREBOOT_BUILD_DAY_BCD, 0x20, |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 84 | COREBOOT_BUILD_YEAR_BCD); |
| 85 | } |
| 86 | |
| 87 | cmos_init(rtc_failed); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | static void setup_mmconfig(void) |
| 91 | { |
| 92 | uint32_t reg; |
| 93 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 94 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 95 | * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the |
| 96 | * config access needs to be used initially to properly configure as the IOSF access |
| 97 | * registers live in PCI config space. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 98 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 99 | reg = 0; |
| 100 | /* Clear the extended register. */ |
| 101 | pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); |
| 102 | reg = CONFIG_MMCONF_BASE_ADDRESS | 1; |
| 103 | pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); |
| 104 | reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | |
| 105 | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; |
| 106 | pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); |
| 107 | } |
| 108 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 109 | void bootblock_soc_early_init(void) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 110 | { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 111 | /* Allow memory-mapped PCI config access */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 112 | setup_mmconfig(); |
| 113 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 114 | /* Early chipset initialization */ |
| 115 | program_base_addresses(); |
| 116 | tco_disable(); |
| 117 | } |
| 118 | void bootblock_soc_init(void) |
| 119 | { |
| 120 | /* Continue chipset initialization */ |
| 121 | soc_rtc_init(); |
| 122 | set_max_freq(); |
| 123 | spi_init(); |
| 124 | |
| 125 | lpc_init(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 126 | } |