soc/intel/braswell: Clean up
Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected.
Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 11bff97..aa8df6b 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -90,11 +90,8 @@
int rtc_failed = rtc_failure();
if (rtc_failed) {
- printk(BIOS_ERR,
- "RTC Failure detected. Resetting date to %x/%x/%x%x\n",
- COREBOOT_BUILD_MONTH_BCD,
- COREBOOT_BUILD_DAY_BCD,
- 0x20,
+ printk(BIOS_ERR, "RTC Failure detected. Resetting date to %x/%x/%x%x\n",
+ COREBOOT_BUILD_MONTH_BCD, COREBOOT_BUILD_DAY_BCD, 0x20,
COREBOOT_BUILD_YEAR_BCD);
}
@@ -106,10 +103,9 @@
uint32_t reg;
/*
- * Set up the MMCONF range. The register lives in the BUNIT. The
- * IO variant of the config access needs to be used initially to
- * properly configure as the IOSF access registers live in PCI
- * config space.
+ * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the
+ * config access needs to be used initially to properly configure as the IOSF access
+ * registers live in PCI config space.
*/
reg = 0;
/* Clear the extended register. */
@@ -124,7 +120,7 @@
void bootblock_soc_early_init(void)
{
- /* Allow memory-mapped PCI config access. */
+ /* Allow memory-mapped PCI config access */
setup_mmconfig();
/* Early chipset initialization */