| Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 1 | config CACHE_MRC_SETTINGS |
| Arthur Heymans | 6ab3eda | 2017-12-18 17:05:14 +0100 | [diff] [blame] | 2 | bool |
| 3 | help |
| 4 | Save cached MRC settings |
| Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 5 | |
| 6 | if CACHE_MRC_SETTINGS |
| 7 | |
| Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 8 | config MRC_SETTINGS_CACHE_SIZE |
| 9 | hex |
| 10 | default 0x10000 |
| 11 | |
| 12 | config MRC_SETTINGS_PROTECT |
| 13 | bool "Enable protection on MRC settings" |
| 14 | default n |
| 15 | |
| 16 | config HAS_RECOVERY_MRC_CACHE |
| 17 | bool |
| 18 | default n |
| 19 | |
| Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 20 | config MRC_SETTINGS_VARIABLE_DATA |
| 21 | bool |
| 22 | default n |
| 23 | |
| Marshall Dawson | f69d2d6 | 2017-12-18 15:56:44 -0700 | [diff] [blame] | 24 | config MRC_WRITE_NV_LATE |
| 25 | bool |
| 26 | default n |
| 27 | help |
| 28 | MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT. |
| 29 | If a platform requires MRC settings written to NVRAM later than |
| 30 | normal, select this item. This will cause the write to occur at |
| 31 | BS_OS_RESUME_CHECK-ENTRY. |
| 32 | |
| Shelley Chen | b4a4f59 | 2020-05-01 17:00:31 -0700 | [diff] [blame] | 33 | config MRC_STASH_TO_CBMEM |
| 34 | bool |
| 35 | default y if MRC_WRITE_NV_LATE || BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES |
| 36 | default n |
| 37 | help |
| 38 | Instead of writing back MRC_CACHE training data back to the |
| 39 | MRC_CACHE right away, stash the data into cbmem. This data |
| 40 | will be written back later to MRC_CACHE. This is selected |
| 41 | for platforms which either do not support writes to SPI |
| 42 | flash in early stages |
| 43 | (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES) or the platforms |
| 44 | that need to write back the MRC data in late ramstage boot |
| 45 | states (MRC_WRITE_NV_LATE). |
| 46 | |
| Shelley Chen | 9f8ac64 | 2020-10-16 12:20:16 -0700 | [diff] [blame] | 47 | config MRC_SAVE_HASH_IN_TPM |
| 48 | bool "Save a hash of the MRC_CACHE data in TPM NVRAM" |
| Michał Żygowski | b5e729c | 2022-05-09 18:22:39 +0200 | [diff] [blame] | 49 | depends on VBOOT_STARTS_IN_BOOTBLOCK && TPM2 && !TPM1 && !VBOOT_MOCK_SECDATA |
| Shelley Chen | 9f8ac64 | 2020-10-16 12:20:16 -0700 | [diff] [blame] | 50 | default y |
| 51 | help |
| 52 | Store a hash of the MRC_CACHE training data in a TPM NVRAM |
| 53 | space to ensure that it cannot be tampered with. |
| 54 | |
| Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 55 | config MRC_CACHE_USING_MRC_VERSION |
| 56 | bool |
| Martin Roth | 09202cc | 2023-08-24 17:19:03 -0600 | [diff] [blame^] | 57 | default y if UDK_VERSION >= 202302 |
| Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 58 | default n |
| 59 | help |
| 60 | Use the MRC version info from FSP extended header to store the MRC cache data. |
| 61 | This method relies on the FSP_PRODUCER_DATA_TABLES belongs to the |
| 62 | `FspProducerDataHeader.h`file to get the MRC version. |
| 63 | |
| 64 | Intel FSP built with EDK2 version 202302 onwards has support to retrieve the |
| 65 | MRC version by directly parsing the binary. |
| 66 | |
| Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 67 | endif # CACHE_MRC_SETTINGS |