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review.coreboot.org / coreboot / 08e0fb881093c977488de6e8d701dd69369123ec / . / src / mainboard / via / pc2500e / mptable.c
blob: e3f1fc15ea0f63bbe723188895fac429141a0b27 [file] [log] [blame]
Jonathan A. Kollasch48994e12008-12-20 04:08:40 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
8 * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25#include <console/console.h>
26#include <arch/smp/mpspec.h>
27#include <device/pci.h>
28#include <string.h>
29#include <stdint.h>
30#include <../../../southbridge/via/vt8237r/vt8237r.h>
31
32
33#define bus_isa 2
34
Myles Watson08e0fb82010-03-22 16:33:25 +0000[diff] [blame^]35static void *smp_write_config_table(void *v)
Jonathan A. Kollasch48994e12008-12-20 04:08:40 +0000[diff] [blame]36{
37 static const char sig[4] = "PCMP";
38 static const char oem[8] = "VIA ";
39 static const char productid[12] = "PC2500 ";
40 struct mp_config_table *mc;
41
42 int bus_num;
43 int i;
44
45 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 memset(mc, 0, sizeof(*mc));
47
48 memcpy(mc->mpc_signature, sig, sizeof(sig));
49 mc->mpc_length = sizeof(*mc); /* initially just the header */
50 mc->mpc_spec = 0x04;
51 mc->mpc_checksum = 0; /* not yet computed */
52 memcpy(mc->mpc_oem, oem, sizeof(oem));
53 memcpy(mc->mpc_productid, productid, sizeof(productid));
54 mc->mpc_oemptr = 0;
55 mc->mpc_oemsize = 0;
56 mc->mpc_entry_count = 0; /* No entries yet... */
57 mc->mpc_lapic = LAPIC_ADDR;
58 mc->mpe_length = 0;
59 mc->mpe_checksum = 0;
60 mc->reserved = 0;
61
62 smp_write_processors(mc);
63
64
65/* Bus: Bus ID Type*/
66 /* define numbers for pci and isa bus */
67 for (bus_num = 0; bus_num < bus_isa; bus_num++) {
68 smp_write_bus(mc, bus_num, "PCI ");
69 }
70 smp_write_bus(mc, bus_isa, "ISA ");
71
72
73/* I/O APICs: APIC ID Version State Address*/
74 smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE);
75
76 /* Now, assemble the table. */
77
78 smp_write_intsrc(mc, mp_ExtINT,
79 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
80 bus_isa, 0x0, VT8237R_APIC_ID, 0x0);
81
82#define ISA_INT(intr, pin) \
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, \
84 bus_isa, (intr), VT8237R_APIC_ID, (pin))
85
86 ISA_INT(1, 1);
87 ISA_INT(0, 2);
88 ISA_INT(3, 3);
89 ISA_INT(4, 4);
90
91 ISA_INT(6, 6);
92 ISA_INT(7, 7);
93 ISA_INT(8, 8);
94 ISA_INT(9, 9);
95
96 ISA_INT(0xc, 0xc);
97 ISA_INT(0xd, 0xd);
98 ISA_INT(0xe, 0xe);
99 ISA_INT(0xf, 0xf);
100
101#define PCI_INT(bus, dev, fn, pin) \
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
103 bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin))
104
105 // PCI slot 1
106 PCI_INT(0, 8, 0, 16);
107 PCI_INT(0, 8, 1, 17);
108 PCI_INT(0, 8, 2, 18);
109 PCI_INT(0, 8, 3, 19);
110
111 // PCI slot 2
112 PCI_INT(0, 9, 0, 17);
113 PCI_INT(0, 9, 1, 18);
114 PCI_INT(0, 9, 2, 19);
115 PCI_INT(0, 9, 3, 16);
116
117 // SATA
118 PCI_INT(0, 15, 1, 20);
119
120 // USB
121 PCI_INT(0, 16, 0, 21);
122 PCI_INT(0, 16, 1, 21);
123 PCI_INT(0, 16, 2, 21);
124 PCI_INT(0, 16, 3, 21);
125
126 // Audio
127 PCI_INT(0, 17, 2, 22);
128
129 // Ethernet
130 PCI_INT(0, 18, 0, 23);
131
132 /* Onboard VGA */
133 PCI_INT(1, 0, 0, 16);
134
135/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
136 smp_write_lintsrc(mc, mp_ExtINT,
137 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
138 0, 0x0, MP_APIC_ALL, 0x0);
139 smp_write_lintsrc(mc, mp_NMI,
140 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
141 0, 0x0, MP_APIC_ALL, 0x1);
142
143 /* There is no extension information... */
144
145 /* Compute the checksums */
146 mc->mpe_checksum =
147 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
148 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]149 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
Jonathan A. Kollasch48994e12008-12-20 04:08:40 +0000[diff] [blame]150 mc, smp_next_mpe_entry(mc));
151 return smp_next_mpe_entry(mc);
152}
153
154unsigned long write_smp_table(unsigned long addr)
155{
156 void *v;
157 v = smp_write_floating_table(addr);
158 return (unsigned long)smp_write_config_table(v);
159}