Ed Swierk | b8e53eb | 2008-10-13 23:18:56 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Arastra, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #define ASSEMBLY 1 |
| 22 | #include <stdint.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <device/pnp_def.h> |
| 28 | #include <arch/romcc_io.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include "pc80/mc146818rtc_early.c" |
| 31 | #include "pc80/serial.c" |
| 32 | #include "pc80/udelay_io.c" |
| 33 | #include "arch/i386/lib/console.c" |
| 34 | #include "ram/ramtest.c" |
| 35 | #include "southbridge/intel/i3100/i3100_early_smbus.c" |
| 36 | #include "southbridge/intel/i3100/i3100_early_lpc.c" |
| 37 | #include "northbridge/intel/i3100/raminit_ep80579.h" |
| 38 | #include "superio/intel/i3100/i3100.h" |
| 39 | #include "cpu/x86/lapic/boot_cpu.c" |
| 40 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 41 | #include "superio/intel/i3100/i3100_early_serial.c" |
| 42 | #include "cpu/x86/bist.h" |
| 43 | #include "spd.h" |
| 44 | |
| 45 | #define SIO_GPIO_BASE 0x680 |
| 46 | #define SIO_XBUS_BASE 0x4880 |
| 47 | |
| 48 | #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) |
| 49 | |
| 50 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 51 | { |
| 52 | /* nothing to do */ |
| 53 | } |
| 54 | static inline int spd_read_byte(u16 device, u8 address) |
| 55 | { |
| 56 | return smbus_read_byte(device, address); |
| 57 | } |
| 58 | |
| 59 | #include "northbridge/intel/i3100/raminit_ep80579.c" |
| 60 | #include "sdram/generic_sdram.c" |
| 61 | #include "../../intel/jarrell/debug.c" |
| 62 | |
| 63 | /* #define TRUXTON_DEBUG */ |
| 64 | |
| 65 | static void main(unsigned long bist) |
| 66 | { |
| 67 | msr_t msr; |
| 68 | u16 perf; |
| 69 | static const struct mem_controller mch[] = { |
| 70 | { |
| 71 | .node_id = 0, |
| 72 | .f0 = PCI_DEV(0, 0x00, 0), |
| 73 | .channel0 = { (0xa<<3)|2, (0xa<<3)|3 }, |
| 74 | } |
| 75 | }; |
| 76 | |
| 77 | if (bist == 0) { |
| 78 | /* Skip this if there was a built in self test failure */ |
| 79 | early_mtrr_init(); |
| 80 | if (memory_initialized()) { |
| 81 | asm volatile ("jmp __cpu_reset"); |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | /* Set up the console */ |
| 86 | i3100_enable_superio(); |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame^] | 87 | i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, CONFIG_TTYS0_BASE); |
Ed Swierk | b8e53eb | 2008-10-13 23:18:56 +0000 | [diff] [blame] | 88 | uart_init(); |
| 89 | console_init(); |
| 90 | |
| 91 | /* Prevent the TCO timer from rebooting us */ |
| 92 | i3100_halt_tco_timer(); |
| 93 | |
| 94 | /* Halt if there was a built in self test failure */ |
| 95 | report_bist_failure(bist); |
| 96 | |
| 97 | #ifdef TRUXTON_DEBUG |
| 98 | print_pci_devices(); |
| 99 | #endif |
| 100 | enable_smbus(); |
| 101 | dump_spd_registers(); |
| 102 | |
| 103 | sdram_initialize(ARRAY_SIZE(mch), mch); |
| 104 | dump_pci_devices(); |
| 105 | dump_pci_device(PCI_DEV(0, 0x00, 0)); |
| 106 | #ifdef TRUXTON_DEBUG |
| 107 | dump_bar14(PCI_DEV(0, 0x00, 0)); |
| 108 | #endif |
| 109 | |
| 110 | #ifdef TRUXTON_DEBUG |
| 111 | ram_fill(0x00000000, 0x02000000); |
| 112 | ram_verify(0x00000000, 0x02000000); |
| 113 | #endif |
| 114 | } |