| Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <arch/asm.h> |
| 23 | #include "../../../../src/northbridge/intel/i945/ich7.h" |
| 24 | |
| 25 | #undef DEBUG_SMM_RELOCATION |
| 26 | //#define DEBUG_SMM_RELOCATION |
| 27 | |
| 28 | #define LAPIC_ID 0xfee00020 |
| 29 | |
| 30 | .global smm_relocation_start |
| 31 | .global smm_relocation_end |
| 32 | |
| 33 | /* initially SMM is some sort of real mode. */ |
| 34 | .code16 |
| 35 | |
| 36 | /** |
| 37 | * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 ) |
| 38 | * |
| 39 | * Why 0x400? It is a safe value to cover the save state area per CPU. On |
| 40 | * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel |
| 41 | * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes |
| 42 | * bigger, effectively sizing our data structures 0x300 bytes. |
| 43 | * |
| 44 | * LAPICID SMBASE SMM Entry SAVE STATE |
| 45 | * 0 0xa0000 0xa8000 0xafd00 |
| 46 | * 1 0x9fc00 0xa7c00 0xaf900 |
| 47 | * 2 0x9f800 0xa7800 0xaf500 |
| 48 | * 3 0x9f400 0xa7400 0xaf100 |
| 49 | * 4 0x9f000 0xa7000 0xaed00 |
| 50 | * 5 0x9ec00 0xa6c00 0xae900 |
| 51 | * 6 0x9e800 0xa6800 0xae500 |
| 52 | * 7 0x9e400 0xa6400 0xae100 |
| 53 | * 8 0x9e000 0xa6000 0xadd00 |
| 54 | * 9 0x9dc00 0xa5c00 0xad900 |
| 55 | * 10 0x9d800 0xa5800 0xad500 |
| 56 | * 11 0x9d400 0xa5400 0xad100 |
| 57 | * 12 0x9d000 0xa5000 0xacd00 |
| 58 | * 13 0x9cc00 0xa4c00 0xac900 |
| 59 | * 14 0x9c800 0xa4800 0xac500 |
| 60 | * 15 0x9c400 0xa4400 0xac100 |
| 61 | * . . . . |
| 62 | * . . . . |
| 63 | * . . . . |
| 64 | * 31 0x98400 0xa0400 0xa8100 |
| 65 | * |
| 66 | * With 32 cores, the SMM handler would need to fit between |
| 67 | * 0xa0000-0xa0400 and the stub plus stack would need to go |
| 68 | * at 0xa8000-0xa8100 (example for core 0). That is not enough. |
| 69 | * |
| 70 | * This means we're basically limited to 16 cpu cores before |
| 71 | * we need to use the TSEG/HSEG for the actual SMM handler plus stack. |
| 72 | * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG. |
| 73 | * |
| 74 | * If we figure out the documented values above are safe to use, |
| 75 | * we could pack the structure above even more, so we could use the |
| 76 | * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs |
| 77 | * in the ASEG. |
| 78 | * |
| 79 | * Note: Some versions of Pentium M need their SMBASE aligned to 32k. |
| 80 | * On those the above only works for up to 2 cores. But for now we only |
| 81 | * care fore Core (2) Duo/Solo |
| 82 | * |
| 83 | */ |
| 84 | |
| 85 | smm_relocation_start: |
| 86 | /* Check revision to see if AMD64 style SMM_BASE |
| 87 | * Intel Core Solo/Duo: 0x30007 |
| 88 | * Intel Core2 Solo/Duo: 0x30100 |
| 89 | * AMD64: 0x3XX64 |
| 90 | * This check does not make much sense, unless someone ports |
| 91 | * SMI handling to AMD64 CPUs. |
| 92 | */ |
| 93 | |
| 94 | mov $0x38000 + 0x7efc, %ebx |
| 95 | addr32 mov (%ebx), %al |
| 96 | cmp $0x64, %al |
| 97 | je 1f |
| 98 | |
| 99 | mov $0x38000 + 0x7ef8, %ebx |
| 100 | jmp smm_relocate |
| 101 | 1: |
| 102 | mov $0x38000 + 0x7f00, %ebx |
| 103 | |
| 104 | smm_relocate: |
| 105 | /* Get this CPU's LAPIC ID */ |
| 106 | movl $LAPIC_ID, %esi |
| 107 | addr32 movl (%esi), %ecx |
| 108 | shr $24, %ecx |
| 109 | |
| 110 | /* calculate offset by multiplying the |
| 111 | * apic ID by 1024 (0x400) |
| 112 | */ |
| 113 | movl %ecx, %edx |
| 114 | shl $10, %edx |
| 115 | |
| 116 | movl $0xa0000, %eax |
| 117 | subl %edx, %eax /* subtract offset, see above */ |
| 118 | |
| 119 | addr32 movl %eax, (%ebx) |
| 120 | |
| 121 | |
| 122 | /* The next section of code is hardware specific */ |
| 123 | |
| 124 | /* Clear SMI status */ |
| 125 | movw $(DEFAULT_PMBASE + 0x34), %dx |
| 126 | inw %dx, %ax |
| 127 | outw %ax, %dx |
| 128 | |
| 129 | /* Clear PM1 status */ |
| 130 | movw $(DEFAULT_PMBASE + 0x00), %dx |
| 131 | inw %dx, %ax |
| 132 | outw %ax, %dx |
| 133 | |
| 134 | /* Set EOS bit so other SMIs can occur */ |
| 135 | movw $(DEFAULT_PMBASE + 0x30), %dx |
| 136 | inl %dx, %eax |
| 137 | orl $(1 << 1), %eax |
| 138 | outl %eax, %dx |
| 139 | |
| 140 | /* End of hardware specific section. */ |
| 141 | #ifdef DEBUG_SMM_RELOCATION |
| 142 | /* print [SMM-x] so we can determine if CPUx went to SMM */ |
| Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame^] | 143 | movw $CONFIG_TTYS0_BASE, %dx |
| Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 144 | mov $'[', %al |
| 145 | outb %al, %dx |
| 146 | mov $'S', %al |
| 147 | outb %al, %dx |
| 148 | mov $'M', %al |
| 149 | outb %al, %dx |
| 150 | outb %al, %dx |
| 151 | movb $'-', %al |
| 152 | outb %al, %dx |
| 153 | /* calculate ascii of cpu number. More than 9 cores? -> FIXME */ |
| 154 | movb %cl, %al |
| 155 | addb $'0', %al |
| 156 | outb %al, %dx |
| 157 | mov $']', %al |
| 158 | outb %al, %dx |
| 159 | mov $'\r', %al |
| 160 | outb %al, %dx |
| 161 | mov $'\n', %al |
| 162 | outb %al, %dx |
| 163 | #endif |
| 164 | |
| 165 | /* That's it. return */ |
| 166 | rsm |
| 167 | smm_relocation_end: |
| 168 | |