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review.coreboot.org / coreboot / 08391d2f5ffea38aa95152c53492f72261786714 / . / util / msrtool / intel_pentium_d.c
blob: 127b1e1d046054abca6867f17f2c63ca0c3b218f [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Elyes HAOUAS6e6b36a2018-05-15 13:28:54 +0200[diff] [blame]2
3#include "msrtool.h"
4
5int intel_pentium_d_probe(const struct targetdef *target, const struct cpuid_t *id) {
6 return ((VENDOR_INTEL == id->vendor) &&
7 (0xf == id->family) &&
8 (0x6 == id->model));
9}
10
11const struct msrdef intel_pentium_d_msrs[] = {
12 {0x0000, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", {
13 { BITS_EOT }
14 }},
15 {0x0001, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", {
16 { BITS_EOT }
17 }},
18 {0x0006, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {
19 { BITS_EOT }
20 }},
21 {0x0010, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {
22 { BITS_EOT }
23 }},
24 {0x0017, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {
25 { BITS_EOT }
26 }},
27 {0x001B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", {
28 { BITS_EOT }
29 }},
30 {0x002A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_HARD_POWERON", "", {
31 { BITS_EOT }
32 }},
33 {0x002B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_SOFT_POWERON", "", {
34 { BITS_EOT }
35 }},
36 {0x002C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_FREQUENCY_ID", "", {
37 { BITS_EOT }
38 }},
39 {0x008B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", {
40 { BITS_EOT }
41 }},
42 {0x00FE, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
43 { BITS_EOT }
44 }},
45 {0x0174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", {
46 { BITS_EOT }
47 }},
48 {0x0175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", {
49 { BITS_EOT }
50 }},
51 {0x0176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", {
52 { BITS_EOT }
53 }},
54 {0x0179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
55 { BITS_EOT }
56 }},
57 {0x017A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
58 { BITS_EOT }
59 }},
60 {0x0180, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RAX", "", {
61 { BITS_EOT }
62 }},
63 {0x0181, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBX", "", {
64 { BITS_EOT }
65 }},
66 {0x0182, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RCX", "", {
67 { BITS_EOT }
68 }},
69 {0x0183, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDX", "", {
70 { BITS_EOT }
71 }},
72 {0x0184, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSI", "", {
73 { BITS_EOT }
74 }},
75 {0x0185, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDI", "", {
76 { BITS_EOT }
77 }},
78 {0x0186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL0", "", {
79 { BITS_EOT }
80 }},
81 {0x0187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL1", "", {
82 { BITS_EOT }
83 }},
84 {0x0188, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RFLAGS", "", {
85 { BITS_EOT }
86 }},
87 {0x0189, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RIP", "", {
88 { BITS_EOT }
89 }},
90 {0x018A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_MISC", "", {
91 { BITS_EOT }
92 }},
93 {0x0190, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R8", "", {
94 { BITS_EOT }
95 }},
96 {0x0191, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R9", "", {
97 { BITS_EOT }
98 }},
99 {0x0192, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R10", "", {
100 { BITS_EOT }
101 }},
102 {0x0193, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R11", "", {
103 { BITS_EOT }
104 }},
105 {0x0194, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R12", "", {
106 { BITS_EOT }
107 }},
108 {0x0195, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R13", "", {
109 { BITS_EOT }
110 }},
111 {0x0196, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R14", "", {
112 { BITS_EOT }
113 }},
114 {0x0197, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R15", "", {
115 { BITS_EOT }
116 }},
117 {0x0198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
118 { BITS_EOT }
119 }},
120 {0x0199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", {
121 { BITS_EOT }
122 }},
123 {0x019A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", {
124 { BITS_EOT }
125 }},
126 {0x019B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", {
127 { BITS_EOT }
128 }},
129 {0x019C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", {
130 { BITS_EOT }
131 }},
132 {0x019D, MSRTYPE_RDWR, MSR2(0, 0), "GV_THERM", "", {
133 { BITS_EOT }
134 }},
135 {0x01A0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", {
136 { BITS_EOT }
137 }},
138 {0x01A1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PLATFORM_BRV", "", {
139 { BITS_EOT }
140 }},
141 {0x01A2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TEMPERATURE_TARGET", "", {
142 { BITS_EOT }
143 }},
144 {0x01D7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", {
145 { BITS_EOT }
146 }},
147 {0x01D8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", {
148 { BITS_EOT }
149 }},
150 {0x01D9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {
151 { BITS_EOT }
152 }},
153 {0x01DA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "", {
154 { BITS_EOT }
155 }},
156 {0x0200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {
157 { BITS_EOT }
158 }},
159 {0x0201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {
160 { BITS_EOT }
161 }},
162 {0x0202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {
163 { BITS_EOT }
164 }},
165 {0x0203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {
166 { BITS_EOT }
167 }},
168 {0x0204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {
169 { BITS_EOT }
170 }},
171 {0x0205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {
172 { BITS_EOT }
173 }},
174 {0x0206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {
175 { BITS_EOT }
176 }},
177 {0x0207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {
178 { BITS_EOT }
179 }},
180 {0x0208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {
181 { BITS_EOT }
182 }},
183 {0x0209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {
184 { BITS_EOT }
185 }},
186 {0x020A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {
187 { BITS_EOT }
188 }},
189 {0x020B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {
190 { BITS_EOT }
191 }},
192 {0x020C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {
193 { BITS_EOT }
194 }},
195 {0x020D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {
196 { BITS_EOT }
197 }},
198 {0x020E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {
199 { BITS_EOT }
200 }},
201 {0x020F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {
202 { BITS_EOT }
203 }},
204 {0x0250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
205 { BITS_EOT }
206 }},
207 {0x0258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
208 { BITS_EOT }
209 }},
210 {0x0259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
211 { BITS_EOT }
212 }},
213 {0x0268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
214 { BITS_EOT }
215 }},
216 {0x0269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
217 { BITS_EOT }
218 }},
219 {0x026A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
220 { BITS_EOT }
221 }},
222 {0x026B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
223 { BITS_EOT }
224 }},
225 {0x026C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
226 { BITS_EOT }
227 }},
228 {0x026D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
229 { BITS_EOT }
230 }},
231 {0x026E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
232 { BITS_EOT }
233 }},
234 {0x026F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
235 { BITS_EOT }
236 }},
237 {0x0277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "", {
238 { BITS_EOT }
239 }},
240 {0x02FF, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {
241 { BITS_EOT }
242 }},
243 {0x0300, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER0", "", {
244 { BITS_EOT }
245 }},
246 {0x0301, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER1", "", {
247 { BITS_EOT }
248 }},
249 {0x0302, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER2", "", {
250 { BITS_EOT }
251 }},
252 {0x0303, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER3", "", {
253 { BITS_EOT }
254 }},
255 {0x0304, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER0", "", {
256 { BITS_EOT }
257 }},
258 {0x0305, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER1", "", {
259 { BITS_EOT }
260 }},
261 {0x0306, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER2", "", {
262 { BITS_EOT }
263 }},
264 {0x0307, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER3", "", {
265 { BITS_EOT }
266 }},
267 {0x0308, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER0", "", {
268 { BITS_EOT }
269 }},
270 {0x0309, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER1", "", {
271 { BITS_EOT }
272 }},
273 {0x030A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "", {
274 { BITS_EOT }
275 }},
276 {0x030B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER3", "", {
277 { BITS_EOT }
278 }},
279 {0x030C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER0", "", {
280 { BITS_EOT }
281 }},
282 {0x030D, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER1", "", {
283 { BITS_EOT }
284 }},
285 {0x030E, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER2", "", {
286 { BITS_EOT }
287 }},
288 {0x030F, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER3", "", {
289 { BITS_EOT }
290 }},
291 {0x0310, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER4", "", {
292 { BITS_EOT }
293 }},
294 {0x0311, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER5", "", {
295 { BITS_EOT }
296 }},
297 {0x0345, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", {
298 { BITS_EOT }
299 }},
300 {0x0360, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR0", "", {
301 { BITS_EOT }
302 }},
303 {0x0361, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR1", "", {
304 { BITS_EOT }
305 }},
306 {0x0362, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR2", "", {
307 { BITS_EOT }
308 }},
309 {0x0363, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR3", "", {
310 { BITS_EOT }
311 }},
312 {0x0364, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR0", "", {
313 { BITS_EOT }
314 }},
315 {0x0365, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR1", "", {
316 { BITS_EOT }
317 }},
318 {0x0366, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR2", "", {
319 { BITS_EOT }
320 }},
321 {0x0367, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR3", "", {
322 { BITS_EOT }
323 }},
324 {0x0368, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR0", "", {
325 { BITS_EOT }
326 }},
327 {0x0369, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR1", "", {
328 { BITS_EOT }
329 }},
330 {0x036A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR2", "", {
331 { BITS_EOT }
332 }},
333 {0x036B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR3", "", {
334 { BITS_EOT }
335 }},
336 {0x036C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR0", "", {
337 { BITS_EOT }
338 }},
339 {0x036D, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR1", "", {
340 { BITS_EOT }
341 }},
342 {0x036E, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR2", "", {
343 { BITS_EOT }
344 }},
345 {0x036F, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR3", "", {
346 { BITS_EOT }
347 }},
348 {0x0370, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR4", "", {
349 { BITS_EOT }
350 }},
351 {0x0371, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR5", "", {
352 { BITS_EOT }
353 }},
354 {0x03A0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR0", "", {
355 { BITS_EOT }
356 }},
357 {0x03A1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR1", "", {
358 { BITS_EOT }
359 }},
360 {0x03A2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR0", "", {
361 { BITS_EOT }
362 }},
363 {0x03A3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR1", "", {
364 { BITS_EOT }
365 }},
366 {0x03A4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR0", "", {
367 { BITS_EOT }
368 }},
369 {0x03A5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR1", "", {
370 { BITS_EOT }
371 }},
372 {0x03A6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR0", "", {
373 { BITS_EOT }
374 }},
375 {0x03A7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR1", "", {
376 { BITS_EOT }
377 }},
378 {0x03A8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR0", "", {
379 { BITS_EOT }
380 }},
381 {0x03A9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR1", "", {
382 { BITS_EOT }
383 }},
384 {0x03AA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR0", "", {
385 { BITS_EOT }
386 }},
387 {0x03AB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR1", "", {
388 { BITS_EOT }
389 }},
390 {0x03AC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR0", "", {
391 { BITS_EOT }
392 }},
393 {0x03AD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR1", "", {
394 { BITS_EOT }
395 }},
396 {0x03AE, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR0", "", {
397 { BITS_EOT }
398 }},
399 {0x03AF, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR1", "", {
400 { BITS_EOT }
401 }},
402 {0x03B0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR0", "", {
403 { BITS_EOT }
404 }},
405 {0x03B1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR1", "", {
406 { BITS_EOT }
407 }},
408 {0x03B2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR0", "", {
409 { BITS_EOT }
410 }},
411 {0x03B3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", {
412 { BITS_EOT }
413 }},
414 {0x03B4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR0", "", {
415 { BITS_EOT }
416 }},
417 {0x03B5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", {
418 { BITS_EOT }
419 }},
420 {0x03B6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR0", "", {
421 { BITS_EOT }
422 }},
423 {0x03B7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR1", "", {
424 { BITS_EOT }
425 }},
426 {0x03B8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR0", "", {
427 { BITS_EOT }
428 }},
429 {0x03B9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR1", "", {
430 { BITS_EOT }
431 }},
432 {0x03BA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR0", "", {
433 { BITS_EOT }
434 }},
435 {0x03BB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR1", "", {
436 { BITS_EOT }
437 }},
438 {0x03BC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR0", "", {
439 { BITS_EOT }
440 }},
441 {0x03BD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR1", "", {
442 { BITS_EOT }
443 }},
444 {0x03BE, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SSU_ESCR0", "", {
445 { BITS_EOT }
446 }},
447 {0x03C0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR0", "", {
448 { BITS_EOT }
449 }},
450 {0x03C1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR1", "", {
451 { BITS_EOT }
452 }},
453 {0x03C2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR0", "", {
454 { BITS_EOT }
455 }},
456 {0x03C3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR1", "", {
457 { BITS_EOT }
458 }},
459 {0x03C4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR0", "", {
460 { BITS_EOT }
461 }},
462 {0x03C5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR1", "", {
463 { BITS_EOT }
464 }},
465 {0x03C8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", {
466 { BITS_EOT }
467 }},
468 {0x03C9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR1", "", {
469 { BITS_EOT }
470 }},
471 {0x03CA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR0", "", {
472 { BITS_EOT }
473 }},
474 {0x03CB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR1", "", {
475 { BITS_EOT }
476 }},
477 {0x03CC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR2", "", {
478 { BITS_EOT }
479 }},
480 {0x03CD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR3", "", {
481 { BITS_EOT }
482 }},
483 {0x03E0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR4", "", {
484 { BITS_EOT }
485 }},
486 {0x03E1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR5", "", {
487 { BITS_EOT }
488 }},
489 {0x03F0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_PRECISE_EVENT", "", {
490 { BITS_EOT }
491 }},
492 {0x03F1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_ENABLE", "", {
493 { BITS_EOT }
494 }},
495 {0x03F2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_MATRIX_VERT", "", {
496 { BITS_EOT }
497 }},
498 {0x0400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
499 { BITS_EOT }
500 }},
501 {0x0401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
502 { BITS_EOT }
503 }},
504 {0x0402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
505 { BITS_EOT }
506 }},
507 {0x0403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", {
508 { BITS_EOT }
509 }},
510 {0x0404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", {
511 { BITS_EOT }
512 }},
513 {0x0405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", {
514 { BITS_EOT }
515 }},
516 {0x0406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", {
517 { BITS_EOT }
518 }},
519 {0x0408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", {
520 { BITS_EOT }
521 }},
522 {0x0409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", {
523 { BITS_EOT }
524 }},
525 {0x040C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
526 { BITS_EOT }
527 }},
528 {0x040D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
529 { BITS_EOT }
530 }},
531 {0x040E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
532 { BITS_EOT }
533 }},
534 {0x040F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", {
535 { BITS_EOT }
536 }},
537 {0x0600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "", {
538 { BITS_EOT }
539 }},
540 { MSR_EOT }
541};