Martin Roth | fb8876d | 2022-08-07 15:12:12 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 3 | #include <stdint.h> |
Elyes HAOUAS | 3b3d085 | 2021-02-01 10:09:40 +0100 | [diff] [blame] | 4 | #include <lib.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 5 | #include <console/console.h> |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Myles Watson | 3426195 | 2010-03-19 02:33:40 +0000 | [diff] [blame] | 7 | |
Kyösti Mälkki | 7336f97 | 2020-06-08 06:05:03 +0300 | [diff] [blame] | 8 | #if ENV_X86 && CONFIG(SSE2) |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 9 | /* Assembler in lib/ is ugly. */ |
| 10 | static void write_phys(uintptr_t addr, u32 value) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 11 | { |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 12 | asm volatile ( |
Eric Biederman | 8d9c123 | 2003-06-17 08:42:17 +0000 | [diff] [blame] | 13 | "movnti %1, (%0)" |
| 14 | : /* outputs */ |
| 15 | : "r" (addr), "r" (value) /* inputs */ |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 16 | ); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 17 | } |
| 18 | |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 19 | static void phys_memory_barrier(void) |
| 20 | { |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 21 | // Needed for movnti |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 22 | asm volatile ("sfence" ::: "memory"); |
| 23 | } |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 24 | #else |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 25 | static void write_phys(uintptr_t addr, u32 value) |
| 26 | { |
Elyes Haouas | 793403c | 2022-12-08 08:50:21 +0100 | [diff] [blame] | 27 | write32p(addr, value); |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 28 | } |
| 29 | |
| 30 | static void phys_memory_barrier(void) |
| 31 | { |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 32 | asm volatile ("" ::: "memory"); |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 33 | } |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 34 | #endif |
Kyösti Mälkki | 321bce4 | 2019-03-20 19:53:44 +0200 | [diff] [blame] | 35 | |
| 36 | static u32 read_phys(uintptr_t addr) |
| 37 | { |
Elyes Haouas | 793403c | 2022-12-08 08:50:21 +0100 | [diff] [blame] | 38 | return read32p(addr); |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 39 | } |
| 40 | |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 41 | /** |
| 42 | * Rotate ones test pattern that access every bit on a 128bit wide |
| 43 | * memory bus. To test most address lines, addresses are scattered |
| 44 | * using 256B, 4kB and 64kB increments. |
| 45 | * |
Martin Roth | 5f066b2 | 2015-01-04 16:47:39 -0700 | [diff] [blame] | 46 | * @param idx Index to test pattern (0=<idx<0x400) |
| 47 | * @param addr Memory to access on idx |
| 48 | * @param value Value to write or read at addr |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 49 | */ |
| 50 | static inline void test_pattern(unsigned short int idx, |
| 51 | unsigned long *addr, unsigned long *value) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 52 | { |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 53 | uint8_t j, k; |
| 54 | |
| 55 | k = (idx >> 8) + 1; |
| 56 | j = (idx >> 4) & 0x0f; |
| 57 | *addr = idx & 0x0f; |
| 58 | *addr |= j << (4*k); |
| 59 | *value = 0x01010101 << (j & 7); |
| 60 | if (j & 8) |
| 61 | *value = ~(*value); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 62 | } |
| 63 | |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 64 | /** |
| 65 | * Simple write-read-verify memory test. See console debug output for |
| 66 | * any dislocated bytes. |
| 67 | * |
Patrick Rudolph | 3dbd284 | 2017-10-27 11:49:29 +0200 | [diff] [blame] | 68 | * Tests 1MiB of memory starting from start. |
| 69 | * |
Martin Roth | 5f066b2 | 2015-01-04 16:47:39 -0700 | [diff] [blame] | 70 | * @param start System memory offset, aligned to 128bytes |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 71 | */ |
Kyösti Mälkki | e1aa983 | 2019-03-23 10:00:31 +0200 | [diff] [blame] | 72 | static int ram_bitset_nodie(uintptr_t start) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 73 | { |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 74 | unsigned long addr, value, value2; |
| 75 | unsigned short int idx; |
| 76 | unsigned char failed, failures; |
| 77 | uint8_t verbose = 0; |
| 78 | |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 79 | printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start); |
Lee Leahy | 35af5c4 | 2017-03-09 17:35:28 -0800 | [diff] [blame] | 80 | for (idx = 0; idx < 0x400; idx += 4) { |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 81 | test_pattern(idx, &addr, &value); |
| 82 | write_phys(start + addr, value); |
| 83 | } |
| 84 | |
| 85 | /* Make sure we don't read before we wrote */ |
| 86 | phys_memory_barrier(); |
| 87 | |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 88 | printk(BIOS_DEBUG, "DRAM bitset verify: 0x%08lx\n", start); |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 89 | failures = 0; |
Lee Leahy | 35af5c4 | 2017-03-09 17:35:28 -0800 | [diff] [blame] | 90 | for (idx = 0; idx < 0x400; idx += 4) { |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 91 | test_pattern(idx, &addr, &value); |
| 92 | value2 = read_phys(start + addr); |
| 93 | |
| 94 | failed = (value2 != value); |
| 95 | failures |= failed; |
Elyes HAOUAS | 1943f37 | 2018-05-04 16:30:39 +0200 | [diff] [blame] | 96 | if (failed && !verbose) { |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 97 | printk(BIOS_ERR, "0x%08lx wr: 0x%08lx rd: 0x%08lx FAIL\n", |
| 98 | start + addr, value, value2); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 99 | } |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 100 | if (verbose) { |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 101 | if ((addr & 0x0f) == 0) |
| 102 | printk(BIOS_DEBUG, "%08lx wr: %08lx rd:", |
| 103 | start + addr, value); |
| 104 | if (failed) |
| 105 | printk(BIOS_DEBUG, " %08lx!", value2); |
| 106 | else |
| 107 | printk(BIOS_DEBUG, " %08lx ", value2); |
| 108 | if ((addr & 0x0f) == 0xc) |
| 109 | printk(BIOS_DEBUG, "\n"); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 110 | } |
| 111 | } |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 112 | if (failures) { |
Martin Roth | 60293e9 | 2022-11-03 18:52:51 -0600 | [diff] [blame] | 113 | post_code(POST_RAM_FAILURE); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 114 | printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); |
Sven Schnelle | 3ad8c54 | 2011-12-02 16:23:06 +0100 | [diff] [blame] | 115 | return 1; |
Richard Smith | ffb7d8a | 2006-04-01 04:10:44 +0000 | [diff] [blame] | 116 | } |
Lee Leahy | 3e1cab4 | 2017-03-10 17:48:31 -0800 | [diff] [blame] | 117 | printk(BIOS_DEBUG, "\nDRAM range verified.\n"); |
Sven Schnelle | 3ad8c54 | 2011-12-02 16:23:06 +0100 | [diff] [blame] | 118 | return 0; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | |
Kyösti Mälkki | e1aa983 | 2019-03-23 10:00:31 +0200 | [diff] [blame] | 122 | void ram_check(uintptr_t start) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 123 | { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 124 | /* |
| 125 | * This is much more of a "Is my DRAM properly configured?" |
| 126 | * test than a "Is my DRAM faulty?" test. Not all bits |
| 127 | * are tested. -Tyson |
| 128 | */ |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 129 | printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start); |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 130 | if (ram_bitset_nodie(start)) |
Sven Schnelle | 3ad8c54 | 2011-12-02 16:23:06 +0100 | [diff] [blame] | 131 | die("DRAM ERROR"); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 132 | printk(BIOS_DEBUG, "Done.\n"); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 133 | } |
| 134 | |
Sven Schnelle | 3ad8c54 | 2011-12-02 16:23:06 +0100 | [diff] [blame] | 135 | |
Kyösti Mälkki | e1aa983 | 2019-03-23 10:00:31 +0200 | [diff] [blame] | 136 | int ram_check_nodie(uintptr_t start) |
Sven Schnelle | 3ad8c54 | 2011-12-02 16:23:06 +0100 | [diff] [blame] | 137 | { |
| 138 | int ret; |
| 139 | /* |
| 140 | * This is much more of a "Is my DRAM properly configured?" |
| 141 | * test than a "Is my DRAM faulty?" test. Not all bits |
| 142 | * are tested. -Tyson |
| 143 | */ |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 144 | printk(BIOS_DEBUG, "Testing DRAM at : %08lx\n", start); |
Sven Schnelle | 3ad8c54 | 2011-12-02 16:23:06 +0100 | [diff] [blame] | 145 | |
Kyösti Mälkki | e77b9a0 | 2012-03-17 08:09:14 +0100 | [diff] [blame] | 146 | ret = ram_bitset_nodie(start); |
Sven Schnelle | 3ad8c54 | 2011-12-02 16:23:06 +0100 | [diff] [blame] | 147 | printk(BIOS_DEBUG, "Done.\n"); |
Sven Schnelle | 3ad8c54 | 2011-12-02 16:23:06 +0100 | [diff] [blame] | 148 | return ret; |
| 149 | } |
| 150 | |
Kyösti Mälkki | e1aa983 | 2019-03-23 10:00:31 +0200 | [diff] [blame] | 151 | int ram_check_noprint_nodie(uintptr_t start) |
Alexandru Gagniuc | 5239ba2 | 2013-06-08 11:32:36 -0500 | [diff] [blame] | 152 | { |
| 153 | unsigned long addr, value, value2; |
| 154 | unsigned short int idx; |
| 155 | unsigned char failed, failures; |
| 156 | |
Lee Leahy | 35af5c4 | 2017-03-09 17:35:28 -0800 | [diff] [blame] | 157 | for (idx = 0; idx < 0x400; idx += 4) { |
Alexandru Gagniuc | 5239ba2 | 2013-06-08 11:32:36 -0500 | [diff] [blame] | 158 | test_pattern(idx, &addr, &value); |
| 159 | write_phys(start + addr, value); |
| 160 | } |
| 161 | |
| 162 | /* Make sure we don't read before we wrote */ |
| 163 | phys_memory_barrier(); |
| 164 | |
| 165 | failures = 0; |
Lee Leahy | 35af5c4 | 2017-03-09 17:35:28 -0800 | [diff] [blame] | 166 | for (idx = 0; idx < 0x400; idx += 4) { |
Alexandru Gagniuc | 5239ba2 | 2013-06-08 11:32:36 -0500 | [diff] [blame] | 167 | test_pattern(idx, &addr, &value); |
| 168 | value2 = read_phys(start + addr); |
| 169 | |
| 170 | failed = (value2 != value); |
| 171 | failures |= failed; |
| 172 | } |
| 173 | return failures; |
| 174 | } |
| 175 | |
Kyösti Mälkki | f5cf60f | 2019-03-18 15:26:48 +0200 | [diff] [blame] | 176 | /* Assumption is 32-bit addressable UC memory at dst. This also executes |
| 177 | * on S3 resume path so target memory must be restored. |
| 178 | */ |
| 179 | void quick_ram_check_or_die(uintptr_t dst) |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 180 | { |
| 181 | int fail = 0; |
| 182 | u32 backup; |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 183 | backup = read_phys(dst); |
| 184 | write_phys(dst, 0x55555555); |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 185 | phys_memory_barrier(); |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 186 | if (read_phys(dst) != 0x55555555) |
Lee Leahy | 35af5c4 | 2017-03-09 17:35:28 -0800 | [diff] [blame] | 187 | fail = 1; |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 188 | write_phys(dst, 0xaaaaaaaa); |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 189 | phys_memory_barrier(); |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 190 | if (read_phys(dst) != 0xaaaaaaaa) |
Lee Leahy | 35af5c4 | 2017-03-09 17:35:28 -0800 | [diff] [blame] | 191 | fail = 1; |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 192 | write_phys(dst, 0x00000000); |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 193 | phys_memory_barrier(); |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 194 | if (read_phys(dst) != 0x00000000) |
Lee Leahy | 35af5c4 | 2017-03-09 17:35:28 -0800 | [diff] [blame] | 195 | fail = 1; |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 196 | write_phys(dst, 0xffffffff); |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 197 | phys_memory_barrier(); |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 198 | if (read_phys(dst) != 0xffffffff) |
Lee Leahy | 35af5c4 | 2017-03-09 17:35:28 -0800 | [diff] [blame] | 199 | fail = 1; |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 200 | |
Kyösti Mälkki | 19652e6 | 2016-06-17 23:31:42 +0300 | [diff] [blame] | 201 | write_phys(dst, backup); |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 202 | if (fail) { |
Martin Roth | 60293e9 | 2022-11-03 18:52:51 -0600 | [diff] [blame] | 203 | post_code(POST_RAM_FAILURE); |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 204 | die("RAM INIT FAILURE!\n"); |
| 205 | } |
| 206 | phys_memory_barrier(); |
| 207 | } |