Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 2 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 5 | #include <arch/romstage.h> |
Angel Pons | 6935648 | 2020-08-03 15:16:12 +0200 | [diff] [blame] | 6 | #include <commonlib/helpers.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 8 | #include <device/device.h> |
| 9 | #include <device/pci_def.h> |
| 10 | #include <console/console.h> |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 11 | #include <cbmem.h> |
| 12 | #include <northbridge/intel/pineview/pineview.h> |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 13 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 14 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 15 | #include <cpu/intel/smm_reloc.h> |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 16 | #include <stdint.h> |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 17 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 18 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 19 | u32 decode_igd_memory_size(const u32 gms) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 20 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 21 | const u32 gmssize[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256}; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 22 | |
| 23 | if (gms > 9) { |
| 24 | printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n"); |
| 25 | return 0; |
| 26 | } |
| 27 | return gmssize[gms] << 10; |
| 28 | } |
| 29 | |
| 30 | /** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ |
| 31 | u32 decode_igd_gtt_size(const u32 gsm) |
| 32 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 33 | const u8 gsmsize[] = {0, 1, 0, 0}; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 34 | |
| 35 | if (gsm > 3) { |
| 36 | printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n"); |
| 37 | return 0; |
| 38 | } |
| 39 | return (u32)(gsmsize[gsm] << 10); |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 40 | } |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 41 | |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 42 | /** Decodes used TSEG size to bytes. */ |
| 43 | static u32 decode_tseg_size(const u32 esmramc) |
| 44 | { |
| 45 | if (!(esmramc & 1)) |
| 46 | return 0; |
| 47 | |
| 48 | switch ((esmramc >> 1) & 3) { |
| 49 | case 0: |
Angel Pons | 6935648 | 2020-08-03 15:16:12 +0200 | [diff] [blame] | 50 | return 1 * MiB; |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 51 | case 1: |
Angel Pons | 6935648 | 2020-08-03 15:16:12 +0200 | [diff] [blame] | 52 | return 2 * MiB; |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 53 | case 2: |
Angel Pons | 6935648 | 2020-08-03 15:16:12 +0200 | [diff] [blame] | 54 | return 8 * MiB; |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 55 | case 3: |
| 56 | default: |
| 57 | die("Bad TSEG setting.\n"); |
| 58 | } |
| 59 | } |
| 60 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 61 | static size_t northbridge_get_tseg_size(void) |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 62 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 63 | const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 64 | return decode_tseg_size(esmramc); |
| 65 | } |
| 66 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 67 | static uintptr_t northbridge_get_tseg_base(void) |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 68 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 69 | return pci_read_config32(HOST_BRIDGE, TSEG); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 70 | } |
| 71 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 72 | /* |
| 73 | * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. |
| 74 | * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 75 | */ |
Arthur Heymans | 340e4b8 | 2019-10-23 17:25:58 +0200 | [diff] [blame] | 76 | void *cbmem_top_chipset(void) |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 77 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 78 | return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 79 | |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 80 | } |
| 81 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 82 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 83 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 84 | *start = northbridge_get_tseg_base(); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 85 | *size = northbridge_get_tseg_size(); |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 86 | } |
| 87 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 88 | void fill_postcar_frame(struct postcar_frame *pcf) |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 89 | { |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 90 | uintptr_t top_of_ram; |
| 91 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 92 | /* |
| 93 | * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both |
| 94 | * CBMEM and the TSEG region. |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 95 | */ |
| 96 | top_of_ram = (uintptr_t)cbmem_top(); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 97 | postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); |
| 98 | postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), |
| 99 | MTRR_TYPE_WRBACK); |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 100 | } |