Angel Pons | 567ece4 | 2022-05-06 21:56:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/pci_def.h> |
| 5 | #include <device/pci_mmio_cfg.h> |
| 6 | #include <device/pci_ops.h> |
| 7 | #include <northbridge/intel/haswell/haswell.h> |
| 8 | #include <northbridge/intel/haswell/vcu_mailbox.h> |
| 9 | #include <types.h> |
| 10 | |
| 11 | #define PEG_DEV(func) PCI_DEV(0, 1, func) |
| 12 | |
| 13 | #define MAX_PEG_FUNC 3 |
| 14 | |
| 15 | static void peg_dmi_unset_and_set_mask_pcicfg( |
| 16 | volatile union pci_bank *const bank, |
| 17 | const uint32_t offset, |
| 18 | const uint32_t unset_mask, |
| 19 | const uint32_t set_mask, |
| 20 | const uint32_t shift, |
| 21 | const bool valid) |
| 22 | { |
| 23 | if (!valid) |
| 24 | return; |
| 25 | |
| 26 | volatile uint32_t *const addr = &bank->reg32[offset / sizeof(uint32_t)]; |
| 27 | clrsetbits32(addr, unset_mask << shift, set_mask << shift); |
| 28 | } |
| 29 | |
| 30 | static void peg_dmi_unset_and_set_mask_common( |
| 31 | const bool is_peg, |
| 32 | const uint32_t offset, |
| 33 | const uint32_t unset, |
| 34 | const uint32_t set, |
| 35 | const uint32_t shift, |
| 36 | const bool valid) |
| 37 | { |
| 38 | const uint32_t unset_mask = unset << shift; |
| 39 | const uint32_t set_mask = set << shift; |
| 40 | if (is_peg) { |
| 41 | for (uint8_t i = 0; i < MAX_PEG_FUNC; i++) |
| 42 | pci_update_config32(PEG_DEV(i), offset, ~unset_mask, set_mask); |
| 43 | } else { |
| 44 | dmibar_clrsetbits32(offset, unset_mask, set_mask); |
| 45 | } |
| 46 | } |
| 47 | |
| 48 | static void peg_dmi_unset_and_set_mask_vcu_mmio( |
| 49 | const uint32_t addr, |
| 50 | const uint32_t unset_mask, |
| 51 | const uint32_t set_mask, |
| 52 | const uint32_t shift, |
| 53 | const bool valid) |
| 54 | { |
| 55 | if (!valid) |
| 56 | return; |
| 57 | |
| 58 | vcu_update_mmio(addr, ~(unset_mask << shift), set_mask << shift); |
| 59 | } |
| 60 | |
| 61 | #define BUNDLE_STEP 0x20 |
| 62 | |
| 63 | static void *const dmibar = (void *)(uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE; |
| 64 | |
| 65 | void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev) |
| 66 | { |
| 67 | const bool always = true; |
| 68 | const bool is_dmi = !is_peg; |
| 69 | |
| 70 | /* Treat DMIBAR and PEG devices the same way */ |
| 71 | volatile union pci_bank *const bank = is_peg ? pci_map_bus(dev) : dmibar; |
| 72 | |
| 73 | const size_t bundles = (is_peg ? 8 : 2) * BUNDLE_STEP; |
| 74 | |
| 75 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) { |
| 76 | /* These are actually per-lane */ |
| 77 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa00 + i, 0x1f, 0x0c, 0, always); |
| 78 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa10 + i, 0x1f, 0x0c, 0, always); |
| 79 | } |
| 80 | |
| 81 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 82 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x02, 0, is_peg); |
| 83 | |
| 84 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 85 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x03, 5, is_peg); |
| 86 | |
| 87 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 88 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x3f, 0x09, 5, always); |
| 89 | |
| 90 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 91 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x0f, 0x05, 21, is_peg); |
| 92 | |
| 93 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 94 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x08, 6, is_peg); |
| 95 | |
| 96 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 97 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x00, 10, always); |
| 98 | |
| 99 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 100 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x07, 0x00, 18, always); |
| 101 | |
| 102 | peg_dmi_unset_and_set_mask_vcu_mmio(0x0c008001, 0x1f, 0x03, 25, is_peg); |
| 103 | peg_dmi_unset_and_set_mask_vcu_mmio(0x0c0c8001, 0x3f, 0x00, 23, is_dmi); |
| 104 | |
| 105 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0xc28, 0x1f, 0x13, 18, always); |
| 106 | |
| 107 | peg_dmi_unset_and_set_mask_common(is_peg, 0xc38, 0x01, 0x00, 6, always); |
| 108 | peg_dmi_unset_and_set_mask_common(is_peg, 0x260, 0x03, 0x02, 0, always); |
| 109 | |
| 110 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 111 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x900 + i, 0x03, 0x00, 26, always); |
| 112 | |
| 113 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 114 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x03, 0x03, 10, always); |
| 115 | |
| 116 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 117 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x1f, 0x07, 25, is_peg); |
| 118 | |
| 119 | for (size_t i = 0; i < bundles; i += BUNDLE_STEP) |
| 120 | peg_dmi_unset_and_set_mask_pcicfg(bank, 0x91c + i, 0x07, 0x05, 27, is_peg); |
| 121 | } |