| Angel Pons | 064c799 | 2020-03-17 23:09:16 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <console/console.h> |
| 15 | #include <device/mmio.h> |
| 16 | #include <types.h> |
| 17 | |
| 18 | #include "sandybridge.h" |
| 19 | |
| 20 | static const char *const ecc_decoder[] = { |
| 21 | "inactive", |
| 22 | "active on IO", |
| 23 | "disabled on IO", |
| 24 | "active", |
| 25 | }; |
| 26 | |
| 27 | #define ON_OFF(val) (((val) & 1) ? "on" : "off") |
| 28 | |
| 29 | /* Print the memory controller configuration as read from the memory controller registers. */ |
| 30 | void report_memory_config(void) |
| 31 | { |
| 32 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 33 | int i; |
| 34 | |
| 35 | addr_decoder_common = MCHBAR32(MAD_CHNL); |
| 36 | addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); |
| 37 | addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); |
| 38 | |
| 39 | const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; |
| 40 | |
| 41 | printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); |
| 42 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 43 | (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); |
| 44 | |
| 45 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 46 | (addr_decoder_common >> 0) & 3, |
| 47 | (addr_decoder_common >> 2) & 3, |
| 48 | (addr_decoder_common >> 4) & 3); |
| 49 | |
| 50 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 51 | u32 ch_conf = addr_decode_ch[i]; |
| 52 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); |
| 53 | printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); |
| 54 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); |
| 55 | printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); |
| 56 | printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", |
| 57 | ((ch_conf >> 0) & 0xff) * 256, |
| 58 | ((ch_conf >> 19) & 1) ? 16 : 8, |
| 59 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 60 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 61 | printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", |
| 62 | ((ch_conf >> 8) & 0xff) * 256, |
| 63 | ((ch_conf >> 20) & 1) ? 16 : 8, |
| 64 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 65 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 66 | } |
| 67 | } |
| 68 | #undef ON_OFF |