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review.coreboot.org / coreboot / 062ef1cca6c1cd70828288181129ba0d0addd4ab / . / src / vendorcode / amd / agesa / f15 / Include / PlatformInstall.h
blob: 7d96fefb765b7eaf3c31011155e4a7aa4ab5c88b [file] [log] [blame]
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 60740 $ @e \$Date: 2011-10-20 19:47:10 -0600 (Thu, 20 Oct 2011) $
15 */
16/*****************************************************************************
17 *
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 *
44 ***************************************************************************/
45
46/*****************************************************************************
47 *
48 * Start processing the user options: First, set default settings
49 *
50 ****************************************************************************/
51
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]52VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
53 //ModuleHeaderSignature
54 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
55 Int32FromChar ('0', '0', '0', '0'),
56 //ModuleIdentifier[8]
57 AGESA_ID,
58 //ModuleVersion[12]
59 AGESA_VERSION_STRING,
60 //ModuleDispatcher
61 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
62 //NextBlock
63 NULL
64};
65
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]66
67/* Process solution defined socket / family installations
68 *
69 * As part of the release package for each image, define the options below to select the
70 * AGESA processor support included in that image.
71 */
72
73/* Default sockets to off */
74#define OPTION_G34_SOCKET_SUPPORT FALSE
75#define OPTION_C32_SOCKET_SUPPORT FALSE
76#define OPTION_G2012_SOCKET_SUPPORT FALSE
77#define OPTION_C2012_SOCKET_SUPPORT FALSE
78#define OPTION_S1G3_SOCKET_SUPPORT FALSE
79#define OPTION_S1G4_SOCKET_SUPPORT FALSE
80#define OPTION_ASB2_SOCKET_SUPPORT FALSE
81#define OPTION_FS1_SOCKET_SUPPORT FALSE
82#define OPTION_FM1_SOCKET_SUPPORT FALSE
83#define OPTION_FM2_SOCKET_SUPPORT FALSE
84#define OPTION_FP1_SOCKET_SUPPORT FALSE
85#define OPTION_FP2_SOCKET_SUPPORT FALSE
86#define OPTION_FT1_SOCKET_SUPPORT FALSE
87#define OPTION_FT2_SOCKET_SUPPORT FALSE
88#define OPTION_AM3_SOCKET_SUPPORT FALSE
89
90/* Default families to off */
91#define OPTION_FAMILY10H FALSE
92#define OPTION_FAMILY12H FALSE
93#define OPTION_FAMILY14H FALSE
94#define OPTION_FAMILY15H FALSE
95#define OPTION_FAMILY15H_MODEL_0x FALSE
96#define OPTION_FAMILY15H_MODEL_1x FALSE
97#define OPTION_FAMILY15H_MODEL_2x FALSE
98
99
100/* Enable the appropriate socket support */
101#ifdef INSTALL_G34_SOCKET_SUPPORT
102 #if INSTALL_G34_SOCKET_SUPPORT == TRUE
103 #undef OPTION_G34_SOCKET_SUPPORT
104 #define OPTION_G34_SOCKET_SUPPORT TRUE
105 #endif
106#endif
107
108#ifdef INSTALL_C32_SOCKET_SUPPORT
109 #if INSTALL_C32_SOCKET_SUPPORT == TRUE
110 #undef OPTION_C32_SOCKET_SUPPORT
111 #define OPTION_C32_SOCKET_SUPPORT TRUE
112 #endif
113#endif
114
115#ifdef INSTALL_G2012_SOCKET_SUPPORT
116 #if INSTALL_G2012_SOCKET_SUPPORT == TRUE
117 #undef OPTION_G2012_SOCKET_SUPPORT
118 #define OPTION_G2012_SOCKET_SUPPORT TRUE
119 #endif
120#endif
121
122#ifdef INSTALL_C2012_SOCKET_SUPPORT
123 #if INSTALL_C2012_SOCKET_SUPPORT == TRUE
124 #undef OPTION_C2012_SOCKET_SUPPORT
125 #define OPTION_C2012_SOCKET_SUPPORT TRUE
126 #endif
127#endif
128
129#ifdef INSTALL_S1G3_SOCKET_SUPPORT
130 #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
131 #undef OPTION_S1G3_SOCKET_SUPPORT
132 #define OPTION_S1G3_SOCKET_SUPPORT TRUE
133 #endif
134#endif
135
136#ifdef INSTALL_S1G4_SOCKET_SUPPORT
137 #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
138 #undef OPTION_S1G4_SOCKET_SUPPORT
139 #define OPTION_S1G4_SOCKET_SUPPORT TRUE
140 #endif
141#endif
142
143#ifdef INSTALL_ASB2_SOCKET_SUPPORT
144 #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
145 #undef OPTION_ASB2_SOCKET_SUPPORT
146 #define OPTION_ASB2_SOCKET_SUPPORT TRUE
147 #endif
148#endif
149
150#ifdef INSTALL_FS1_SOCKET_SUPPORT
151 #if INSTALL_FS1_SOCKET_SUPPORT == TRUE
152 #undef OPTION_FS1_SOCKET_SUPPORT
153 #define OPTION_FS1_SOCKET_SUPPORT TRUE
154 #endif
155#endif
156
157#ifdef INSTALL_FM1_SOCKET_SUPPORT
158 #if INSTALL_FM1_SOCKET_SUPPORT == TRUE
159 #undef OPTION_FM1_SOCKET_SUPPORT
160 #define OPTION_FM1_SOCKET_SUPPORT TRUE
161 #endif
162#endif
163
164#ifdef INSTALL_FM2_SOCKET_SUPPORT
165 #if INSTALL_FM2_SOCKET_SUPPORT == TRUE
166 #undef OPTION_FM2_SOCKET_SUPPORT
167 #define OPTION_FM2_SOCKET_SUPPORT TRUE
168 #endif
169#endif
170
171#ifdef INSTALL_FP1_SOCKET_SUPPORT
172 #if INSTALL_FP1_SOCKET_SUPPORT == TRUE
173 #undef OPTION_FP1_SOCKET_SUPPORT
174 #define OPTION_FP1_SOCKET_SUPPORT TRUE
175 #endif
176#endif
177
178#ifdef INSTALL_FP2_SOCKET_SUPPORT
179 #if INSTALL_FP2_SOCKET_SUPPORT == TRUE
180 #undef OPTION_FP2_SOCKET_SUPPORT
181 #define OPTION_FP2_SOCKET_SUPPORT TRUE
182 #endif
183#endif
184
185#ifdef INSTALL_FT1_SOCKET_SUPPORT
186 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
187 #undef OPTION_FT1_SOCKET_SUPPORT
188 #define OPTION_FT1_SOCKET_SUPPORT TRUE
189 #endif
190#endif
191
192#ifdef INSTALL_FT2_SOCKET_SUPPORT
193 #if INSTALL_FT2_SOCKET_SUPPORT == TRUE
194 #undef OPTION_FT2_SOCKET_SUPPORT
195 #define OPTION_FT2_SOCKET_SUPPORT TRUE
196 #endif
197#endif
198
199#ifdef INSTALL_AM3_SOCKET_SUPPORT
200 #if INSTALL_AM3_SOCKET_SUPPORT == TRUE
201 #undef OPTION_AM3_SOCKET_SUPPORT
202 #define OPTION_AM3_SOCKET_SUPPORT TRUE
203 #endif
204#endif
205
206
207/* Enable the appropriate family support */
208// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
209#ifdef INSTALL_FAMILY_10_SUPPORT
210 #if INSTALL_FAMILY_10_SUPPORT == TRUE
211 #undef OPTION_FAMILY10H
212 #define OPTION_FAMILY10H TRUE
213 #endif
214#endif
215
216// F12 is supported in FP1, FS1, & FM1
217#ifdef INSTALL_FAMILY_12_SUPPORT
218 #if INSTALL_FAMILY_12_SUPPORT == TRUE
219 #undef OPTION_FAMILY12H
220 #define OPTION_FAMILY12H TRUE
221 #endif
222#endif
223
224// F14 is supported in FT1 and FT2
225#ifdef INSTALL_FAMILY_14_SUPPORT
226 #if INSTALL_FAMILY_14_SUPPORT == TRUE
227 #undef OPTION_FAMILY14H
228 #define OPTION_FAMILY14H TRUE
229 #endif
230#endif
231
232// F15_0x is supported in G34, C32, & AM3
233#ifdef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
234 #if INSTALL_FAMILY_15_MODEL_0x_SUPPORT == TRUE
235 #undef OPTION_FAMILY15H
236 #define OPTION_FAMILY15H TRUE
237 #undef OPTION_FAMILY15H_MODEL_0x
238 #define OPTION_FAMILY15H_MODEL_0x TRUE
239 #endif
240#endif
241
242// F15_1x is supported in FS1r2, FM2, & FP2
243#ifdef INSTALL_FAMILY_15_MODEL_1x_SUPPORT
244 #if INSTALL_FAMILY_15_MODEL_1x_SUPPORT == TRUE
245 #undef OPTION_FAMILY15H
246 #define OPTION_FAMILY15H TRUE
247 #undef OPTION_FAMILY15H_MODEL_1x
248 #define OPTION_FAMILY15H_MODEL_1x TRUE
249 #endif
250#endif
251
252// F15_2x is supported in G2012, C2012, & FM2
253#ifdef INSTALL_FAMILY_15_MODEL_2x_SUPPORT
254 #if INSTALL_FAMILY_15_MODEL_2x_SUPPORT == TRUE
255 #undef OPTION_FAMILY15H
256 #define OPTION_FAMILY15H TRUE
257 #undef OPTION_FAMILY15H_MODEL_2x
258 #define OPTION_FAMILY15H_MODEL_2x TRUE
259 #endif
260#endif
261
262
263/* Turn off families not required by socket designations */
264#if (OPTION_FAMILY10H == TRUE)
265 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
266 #undef OPTION_FAMILY10H
267 #define OPTION_FAMILY10H FALSE
268 #endif
269#endif
270
271#if (OPTION_FAMILY12H == TRUE)
272 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
273 #undef OPTION_FAMILY12H
274 #define OPTION_FAMILY12H FALSE
275 #endif
276#endif
277
278#if (OPTION_FAMILY14H == TRUE)
279 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) && (OPTION_FT2_SOCKET_SUPPORT == FALSE)
280 #undef OPTION_FAMILY14H
281 #define OPTION_FAMILY14H FALSE
282 #endif
283#endif
284
285#if (OPTION_FAMILY15H_MODEL_0x == TRUE)
286 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
287 #undef OPTION_FAMILY15H_MODEL_0x
288 #define OPTION_FAMILY15H_MODEL_0x FALSE
289 #endif
290#endif
291
292#if (OPTION_FAMILY15H_MODEL_1x == TRUE)
293 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE) && (OPTION_FP2_SOCKET_SUPPORT == FALSE)
294 #undef OPTION_FAMILY15H_MODEL_1x
295 #define OPTION_FAMILY15H_MODEL_1x FALSE
296 #endif
297#endif
298
299#if (OPTION_FAMILY15H_MODEL_2x == TRUE)
300 #if (OPTION_G2012_SOCKET_SUPPORT == FALSE) && (OPTION_C2012_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE)
301 #undef OPTION_FAMILY15H_MODEL_2x
302 #define OPTION_FAMILY15H_MODEL_2x FALSE
303 #endif
304#endif
305
306#if (OPTION_FAMILY15H_MODEL_0x == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE) && (OPTION_FAMILY15H_MODEL_2x == FALSE)
307 #undef OPTION_FAMILY15H
308 #define OPTION_FAMILY15H FALSE
309#endif
310
311/* Check for invalid combinations of socket/family */
312#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
313 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
314 #error No G34 supported families included in the build
315 #endif
316#endif
317
318#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
319 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
320 #error No C32 supported families included in the build
321 #endif
322#endif
323
324#if (OPTION_G2012_SOCKET_SUPPORT == TRUE)
325 #if (OPTION_FAMILY15H_MODEL_2x == FALSE)
326 #error No G2012 supported families included in the build
327 #endif
328#endif
329
330#if (OPTION_C2012_SOCKET_SUPPORT == TRUE)
331 #if (OPTION_FAMILY15H_MODEL_2x == FALSE)
332 #error No C2012 supported families included in the build
333 #endif
334#endif
335
336#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
337 #if (OPTION_FAMILY10H == FALSE)
338 #error No S1G3 supported families included in the build
339 #endif
340#endif
341
342#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
343 #if (OPTION_FAMILY10H == FALSE)
344 #error No S1G4 supported families included in the build
345 #endif
346#endif
347
348#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
349 #if (OPTION_FAMILY10H == FALSE)
350 #error No ASB2 supported families included in the build
351 #endif
352#endif
353
354#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
355 #if (OPTION_FAMILY12H == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE)
356 #error No FS1 supported families included in the build
357 #endif
358#endif
359
360#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
361 #if (OPTION_FAMILY12H == FALSE)
362 #error No FM1 supported families included in the build
363 #endif
364#endif
365
366#if (OPTION_FM2_SOCKET_SUPPORT == TRUE)
367 #if (OPTION_FAMILY15H_MODEL_1x == FALSE) && (OPTION_FAMILY15H_MODEL_2x == FALSE)
368 #error No FM2 supported families included in the build
369 #endif
370#endif
371
372#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
373 #if (OPTION_FAMILY12H == FALSE)
374 #error No FP1 supported families included in the build
375 #endif
376#endif
377
378#if (OPTION_FP2_SOCKET_SUPPORT == TRUE)
379 #if (OPTION_FAMILY15H_MODEL_1x == FALSE)
380 #error No FP2 supported families included in the build
381 #endif
382#endif
383
384#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
385 #if (OPTION_FAMILY14H == FALSE)
386 #error No FT1 supported families included in the build
387 #endif
388#endif
389
390#if (OPTION_FT2_SOCKET_SUPPORT == TRUE)
391 #if (OPTION_FAMILY14H == FALSE)
392 #error No FT2 supported families included in the build
393 #endif
394#endif
395
396#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
397 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
398 #error No AM3 supported families included in the build
399 #endif
400#endif
401
402
403/* Process AGESA private data
404 *
405 * Turn on appropriate CPU models and memory controllers,
406 * as well as some other memory controls.
407 */
408
409/* Default all models to off */
410#define OPTION_FAMILY10H_BL FALSE
411#define OPTION_FAMILY10H_DA FALSE
412#define OPTION_FAMILY10H_HY FALSE
413#define OPTION_FAMILY10H_PH FALSE
414#define OPTION_FAMILY10H_RB FALSE
415#define OPTION_FAMILY12H_LN FALSE
416#define OPTION_FAMILY14H_ON FALSE
417#define OPTION_FAMILY14H_KR FALSE
418#define OPTION_FAMILY15H_OR FALSE
419#define OPTION_FAMILY15H_TN FALSE
420#define OPTION_FAMILY15H_KM FALSE
421
422/* Default all memory controllers to off */
423#define OPTION_MEMCTLR_DR FALSE
424#define OPTION_MEMCTLR_HY FALSE
425#define OPTION_MEMCTLR_OR FALSE
426#define OPTION_MEMCTLR_C32 FALSE
427#define OPTION_MEMCTLR_DA FALSE
428#define OPTION_MEMCTLR_LN FALSE
429#define OPTION_MEMCTLR_ON FALSE
430#define OPTION_MEMCTLR_KR FALSE
431#define OPTION_MEMCTLR_Ni FALSE
432#define OPTION_MEMCTLR_PH FALSE
433#define OPTION_MEMCTLR_RB FALSE
434#define OPTION_MEMCTLR_TN FALSE
435#define OPTION_MEMCTLR_KM FALSE
436
437/* Default all memory controls to off */
438#define OPTION_HW_WRITE_LEV_TRAINING FALSE
439#define OPTION_SW_WRITE_LEV_TRAINING FALSE
440#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
441#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
442#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
443#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
444#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
445#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
446#define OPTION_MAX_RD_LAT_TRAINING FALSE
447#define OPTION_HW_DRAM_INIT FALSE
448#define OPTION_SW_DRAM_INIT FALSE
449#define OPTION_S3_MEM_SUPPORT FALSE
450#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
451#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
452#define OPTION_RDDQS____TRAINING FALSE
453
454/* Defaults for public user options */
455#define OPTION_UDIMMS FALSE
456#define OPTION_RDIMMS FALSE
457#define OPTION_SODIMMS FALSE
458#define OPTION_LRDIMMS FALSE
459#define OPTION_DDR2 FALSE
460#define OPTION_DDR3 FALSE
461#define OPTION_ECC FALSE
462#define OPTION_BANK_INTERLEAVE FALSE
463#define OPTION_DCT_INTERLEAVE FALSE
464#define OPTION_NODE_INTERLEAVE FALSE
465#define OPTION_PARALLEL_TRAINING FALSE
466#define OPTION_ONLINE_SPARE FALSE
467#define OPTION_MEM_RESTORE FALSE
468#define OPTION_DIMM_EXCLUDE FALSE
469
470/* Default all CPU controls to off */
471#define OPTION_MULTISOCKET FALSE
472#define OPTION_SRAT FALSE
473#define OPTION_SLIT FALSE
474#define OPTION_HT_ASSIST FALSE
475#define OPTION_ATM_MODE FALSE
476#define OPTION_CPU_CORELEVLING FALSE
477#define OPTION_MSG_BASED_C1E FALSE
478#define OPTION_CPU_CFOH FALSE
479#define OPTION_C6_STATE FALSE
480#define OPTION_IO_CSTATE FALSE
481#define OPTION_CPB FALSE
482#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
483#define OPTION_CPU_PSTATE_HPC_MODE FALSE
484#define OPTION_CPU_APM FALSE
485#define OPTION_S3SCRIPT FALSE
486#define OPTION_GFX_RECOVERY FALSE
487
488/* Default FCH controls to off */
489#define FCH_SUPPORT FALSE
490
491/* Enable all private controls based on socket/family enables */
492#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
493 #if (OPTION_FAMILY10H == TRUE)
494 #undef OPTION_FAMILY10H_HY
495 #define OPTION_FAMILY10H_HY TRUE
496 #undef OPTION_MEMCTLR_HY
497 #define OPTION_MEMCTLR_HY TRUE
498 #undef OPTION_HW_WRITE_LEV_TRAINING
499 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
500 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
501 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
502 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
503 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
504 #undef OPTION_MAX_RD_LAT_TRAINING
505 #define OPTION_MAX_RD_LAT_TRAINING TRUE
506 #undef OPTION_SW_DRAM_INIT
507 #define OPTION_SW_DRAM_INIT TRUE
508 #undef OPTION_S3_MEM_SUPPORT
509 #define OPTION_S3_MEM_SUPPORT TRUE
510 #undef OPTION_MULTISOCKET
511 #define OPTION_MULTISOCKET TRUE
512 #undef OPTION_SRAT
513 #define OPTION_SRAT TRUE
514 #undef OPTION_SLIT
515 #define OPTION_SLIT TRUE
516 #undef OPTION_HT_ASSIST
517 #define OPTION_HT_ASSIST TRUE
518 #undef OPTION_CPU_CORELEVLING
519 #define OPTION_CPU_CORELEVLING TRUE
520 #undef OPTION_MSG_BASED_C1E
521 #define OPTION_MSG_BASED_C1E TRUE
522 #undef OPTION_CPU_CFOH
523 #define OPTION_CPU_CFOH TRUE
524 #undef OPTION_UDIMMS
525 #define OPTION_UDIMMS TRUE
526 #undef OPTION_RDIMMS
527 #define OPTION_RDIMMS TRUE
528 #undef OPTION_SODIMMS
529 #define OPTION_SODIMMS TRUE
530 #undef OPTION_DDR3
531 #define OPTION_DDR3 TRUE
532 #undef OPTION_ECC
533 #define OPTION_ECC TRUE
534 #undef OPTION_BANK_INTERLEAVE
535 #define OPTION_BANK_INTERLEAVE TRUE
536 #undef OPTION_DCT_INTERLEAVE
537 #define OPTION_DCT_INTERLEAVE TRUE
538 #undef OPTION_NODE_INTERLEAVE
539 #define OPTION_NODE_INTERLEAVE TRUE
540 #undef OPTION_PARALLEL_TRAINING
541 #define OPTION_PARALLEL_TRAINING TRUE
542 #undef OPTION_MEM_RESTORE
543 #define OPTION_MEM_RESTORE TRUE
544 #undef OPTION_ONLINE_SPARE
545 #define OPTION_ONLINE_SPARE TRUE
546 #undef OPTION_DIMM_EXCLUDE
547 #define OPTION_DIMM_EXCLUDE TRUE
548 #endif
549 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
550 #undef OPTION_FAMILY15H_OR
551 #define OPTION_FAMILY15H_OR TRUE
552 #undef OPTION_MEMCTLR_OR
553 #define OPTION_MEMCTLR_OR TRUE
554 #undef OPTION_HW_WRITE_LEV_TRAINING
555 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
556 #undef OPTION_CONTINOUS_PATTERN_GENERATION
557 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
558 #undef OPTION_HW_DQS_REC_EN_TRAINING
559 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
560 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
561 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
562 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
563 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
564 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
565 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
566 #undef OPTION_MAX_RD_LAT_TRAINING
567 #define OPTION_MAX_RD_LAT_TRAINING TRUE
568 #undef OPTION_SW_DRAM_INIT
569 #define OPTION_SW_DRAM_INIT TRUE
570 #undef OPTION_S3_MEM_SUPPORT
571 #define OPTION_S3_MEM_SUPPORT TRUE
572 #undef OPTION_MULTISOCKET
573 #define OPTION_MULTISOCKET TRUE
574 #undef OPTION_C6_STATE
575 #define OPTION_C6_STATE TRUE
576 #undef OPTION_IO_CSTATE
577 #define OPTION_IO_CSTATE TRUE
578 #undef OPTION_CPB
579 #define OPTION_CPB TRUE
580 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
581 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
582 #undef OPTION_CPU_APM
583 #define OPTION_CPU_APM TRUE
584 #undef OPTION_SRAT
585 #define OPTION_SRAT TRUE
586 #undef OPTION_SLIT
587 #define OPTION_SLIT TRUE
588 #undef OPTION_HT_ASSIST
589 #define OPTION_HT_ASSIST TRUE
590 #undef OPTION_ATM_MODE
591 #define OPTION_ATM_MODE TRUE
592 #undef OPTION_CPU_CORELEVLING
593 #define OPTION_CPU_CORELEVLING TRUE
594 #undef OPTION_MSG_BASED_C1E
595 #define OPTION_MSG_BASED_C1E TRUE
596 #undef OPTION_CPU_CFOH
597 #define OPTION_CPU_CFOH TRUE
598 #undef OPTION_UDIMMS
599 #define OPTION_UDIMMS TRUE
600 #undef OPTION_RDIMMS
601 #define OPTION_RDIMMS TRUE
602 #undef OPTION_SODIMMS
603 #define OPTION_SODIMMS TRUE
604 #undef OPTION_LRDIMMS
605 #define OPTION_LRDIMMS TRUE
606 #undef OPTION_DDR3
607 #define OPTION_DDR3 TRUE
608 #undef OPTION_ECC
609 #define OPTION_ECC TRUE
610 #undef OPTION_BANK_INTERLEAVE
611 #define OPTION_BANK_INTERLEAVE TRUE
612 #undef OPTION_DCT_INTERLEAVE
613 #define OPTION_DCT_INTERLEAVE TRUE
614 #undef OPTION_NODE_INTERLEAVE
615 #define OPTION_NODE_INTERLEAVE TRUE
616 #undef OPTION_MEM_RESTORE
617 #define OPTION_MEM_RESTORE TRUE
618 #undef OPTION_ONLINE_SPARE
619 #define OPTION_ONLINE_SPARE TRUE
620 #undef OPTION_DIMM_EXCLUDE
621 #define OPTION_DIMM_EXCLUDE TRUE
622 #endif
623#endif
624
625#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
626 #if (OPTION_FAMILY10H == TRUE)
627 #undef OPTION_FAMILY10H_HY
628 #define OPTION_FAMILY10H_HY TRUE
629 #undef OPTION_MEMCTLR_C32
630 #define OPTION_MEMCTLR_C32 TRUE
631 #undef OPTION_HW_WRITE_LEV_TRAINING
632 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
633 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
634 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
635 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
636 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
637 #undef OPTION_MAX_RD_LAT_TRAINING
638 #define OPTION_MAX_RD_LAT_TRAINING TRUE
639 #undef OPTION_SW_DRAM_INIT
640 #define OPTION_SW_DRAM_INIT TRUE
641 #undef OPTION_S3_MEM_SUPPORT
642 #define OPTION_S3_MEM_SUPPORT TRUE
643 #undef OPTION_ADDR_TO_CS_TRANSLATOR
644 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
645 #undef OPTION_MULTISOCKET
646 #define OPTION_MULTISOCKET TRUE
647 #undef OPTION_SRAT
648 #define OPTION_SRAT TRUE
649 #undef OPTION_SLIT
650 #define OPTION_SLIT TRUE
651 #undef OPTION_HT_ASSIST
652 #define OPTION_HT_ASSIST TRUE
653 #undef OPTION_CPU_CORELEVLING
654 #define OPTION_CPU_CORELEVLING TRUE
655 #undef OPTION_MSG_BASED_C1E
656 #define OPTION_MSG_BASED_C1E TRUE
657 #undef OPTION_CPU_CFOH
658 #define OPTION_CPU_CFOH TRUE
659 #undef OPTION_UDIMMS
660 #define OPTION_UDIMMS TRUE
661 #undef OPTION_RDIMMS
662 #define OPTION_RDIMMS TRUE
663 #undef OPTION_SODIMMS
664 #define OPTION_SODIMMS TRUE
665 #undef OPTION_DDR3
666 #define OPTION_DDR3 TRUE
667 #undef OPTION_ECC
668 #define OPTION_ECC TRUE
669 #undef OPTION_BANK_INTERLEAVE
670 #define OPTION_BANK_INTERLEAVE TRUE
671 #undef OPTION_DCT_INTERLEAVE
672 #define OPTION_DCT_INTERLEAVE TRUE
673 #undef OPTION_NODE_INTERLEAVE
674 #define OPTION_NODE_INTERLEAVE TRUE
675 #undef OPTION_PARALLEL_TRAINING
676 #define OPTION_PARALLEL_TRAINING TRUE
677 #undef OPTION_MEM_RESTORE
678 #define OPTION_MEM_RESTORE TRUE
679 #undef OPTION_ONLINE_SPARE
680 #define OPTION_ONLINE_SPARE TRUE
681 #undef OPTION_DIMM_EXCLUDE
682 #define OPTION_DIMM_EXCLUDE TRUE
683 #endif
684 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
685 #undef OPTION_FAMILY15H_OR
686 #define OPTION_FAMILY15H_OR TRUE
687 #undef OPTION_MEMCTLR_OR
688 #define OPTION_MEMCTLR_OR TRUE
689 #undef OPTION_HW_WRITE_LEV_TRAINING
690 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
691 #undef OPTION_CONTINOUS_PATTERN_GENERATION
692 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
693 #undef OPTION_HW_DQS_REC_EN_TRAINING
694 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
695 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
696 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
697 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
698 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
699 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
700 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
701 #undef OPTION_MAX_RD_LAT_TRAINING
702 #define OPTION_MAX_RD_LAT_TRAINING TRUE
703 #undef OPTION_SW_DRAM_INIT
704 #define OPTION_SW_DRAM_INIT TRUE
705 #undef OPTION_S3_MEM_SUPPORT
706 #define OPTION_S3_MEM_SUPPORT TRUE
707 #undef OPTION_ADDR_TO_CS_TRANSLATOR
708 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
709 #undef OPTION_MULTISOCKET
710 #define OPTION_MULTISOCKET TRUE
711 #undef OPTION_C6_STATE
712 #define OPTION_C6_STATE TRUE
713 #undef OPTION_IO_CSTATE
714 #define OPTION_IO_CSTATE TRUE
715 #undef OPTION_CPB
716 #define OPTION_CPB TRUE
717 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
718 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
719 #undef OPTION_CPU_APM
720 #define OPTION_CPU_APM TRUE
721 #undef OPTION_SRAT
722 #define OPTION_SRAT TRUE
723 #undef OPTION_SLIT
724 #define OPTION_SLIT TRUE
725 #undef OPTION_HT_ASSIST
726 #define OPTION_HT_ASSIST TRUE
727 #undef OPTION_ATM_MODE
728 #define OPTION_ATM_MODE TRUE
729 #undef OPTION_CPU_CORELEVLING
730 #define OPTION_CPU_CORELEVLING TRUE
731 #undef OPTION_MSG_BASED_C1E
732 #define OPTION_MSG_BASED_C1E TRUE
733 #undef OPTION_CPU_CFOH
734 #define OPTION_CPU_CFOH TRUE
735 #undef OPTION_UDIMMS
736 #define OPTION_UDIMMS TRUE
737 #undef OPTION_RDIMMS
738 #define OPTION_RDIMMS TRUE
739 #undef OPTION_SODIMMS
740 #define OPTION_SODIMMS TRUE
741 #undef OPTION_LRDIMMS
742 #define OPTION_LRDIMMS TRUE
743 #undef OPTION_DDR3
744 #define OPTION_DDR3 TRUE
745 #undef OPTION_ECC
746 #define OPTION_ECC TRUE
747 #undef OPTION_BANK_INTERLEAVE
748 #define OPTION_BANK_INTERLEAVE TRUE
749 #undef OPTION_DCT_INTERLEAVE
750 #define OPTION_DCT_INTERLEAVE TRUE
751 #undef OPTION_NODE_INTERLEAVE
752 #define OPTION_NODE_INTERLEAVE TRUE
753 #undef OPTION_MEM_RESTORE
754 #define OPTION_MEM_RESTORE TRUE
755 #undef OPTION_ONLINE_SPARE
756 #define OPTION_ONLINE_SPARE TRUE
757 #undef OPTION_DIMM_EXCLUDE
758 #define OPTION_DIMM_EXCLUDE TRUE
759 #endif
760#endif
761
762#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
763 #if (OPTION_FAMILY10H == TRUE)
764 #undef OPTION_FAMILY10H_BL
765 #define OPTION_FAMILY10H_BL TRUE
766 #undef OPTION_FAMILY10H_DA
767 #define OPTION_FAMILY10H_DA TRUE
768 #undef OPTION_MEMCTLR_DA
769 #define OPTION_MEMCTLR_DA TRUE
770 #undef OPTION_HW_WRITE_LEV_TRAINING
771 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
772 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
773 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
774 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
775 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
776 #undef OPTION_MAX_RD_LAT_TRAINING
777 #define OPTION_MAX_RD_LAT_TRAINING TRUE
778 #undef OPTION_SW_DRAM_INIT
779 #define OPTION_SW_DRAM_INIT TRUE
780 #undef OPTION_S3_MEM_SUPPORT
781 #define OPTION_S3_MEM_SUPPORT TRUE
782 #undef OPTION_CPU_CORELEVLING
783 #define OPTION_CPU_CORELEVLING TRUE
784 #undef OPTION_CPU_CFOH
785 #define OPTION_CPU_CFOH TRUE
786 #undef OPTION_UDIMMS
787 #define OPTION_UDIMMS TRUE
788 #undef OPTION_SODIMMS
789 #define OPTION_SODIMMS TRUE
790 #undef OPTION_DDR3
791 #define OPTION_DDR3 TRUE
792 #undef OPTION_ECC
793 #define OPTION_ECC TRUE
794 #undef OPTION_BANK_INTERLEAVE
795 #define OPTION_BANK_INTERLEAVE TRUE
796 #undef OPTION_DCT_INTERLEAVE
797 #define OPTION_DCT_INTERLEAVE TRUE
798 #undef OPTION_NODE_INTERLEAVE
799 #define OPTION_NODE_INTERLEAVE TRUE
800 #undef OPTION_PARALLEL_TRAINING
801 #define OPTION_PARALLEL_TRAINING TRUE
802 #undef OPTION_MEM_RESTORE
803 #define OPTION_MEM_RESTORE TRUE
804 #undef OPTION_ONLINE_SPARE
805 #define OPTION_ONLINE_SPARE TRUE
806 #undef OPTION_DIMM_EXCLUDE
807 #define OPTION_DIMM_EXCLUDE TRUE
808 #endif
809#endif
810
811#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
812 #if (OPTION_FAMILY10H == TRUE)
813 #undef OPTION_FAMILY10H_BL
814 #define OPTION_FAMILY10H_BL TRUE
815 #undef OPTION_FAMILY10H_DA
816 #define OPTION_FAMILY10H_DA TRUE
817 #undef OPTION_MEMCTLR_DA
818 #define OPTION_MEMCTLR_DA TRUE
819 #undef OPTION_HW_WRITE_LEV_TRAINING
820 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
821 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
822 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
823 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
824 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
825 #undef OPTION_MAX_RD_LAT_TRAINING
826 #define OPTION_MAX_RD_LAT_TRAINING TRUE
827 #undef OPTION_SW_DRAM_INIT
828 #define OPTION_SW_DRAM_INIT TRUE
829 #undef OPTION_S3_MEM_SUPPORT
830 #define OPTION_S3_MEM_SUPPORT TRUE
831 #undef OPTION_CPU_CORELEVLING
832 #define OPTION_CPU_CORELEVLING TRUE
833 #undef OPTION_CPU_CFOH
834 #define OPTION_CPU_CFOH TRUE
835 #undef OPTION_UDIMMS
836 #define OPTION_UDIMMS TRUE
837 #undef OPTION_SODIMMS
838 #define OPTION_SODIMMS TRUE
839 #undef OPTION_DDR3
840 #define OPTION_DDR3 TRUE
841 #undef OPTION_ECC
842 #define OPTION_ECC TRUE
843 #undef OPTION_BANK_INTERLEAVE
844 #define OPTION_BANK_INTERLEAVE TRUE
845 #undef OPTION_DCT_INTERLEAVE
846 #define OPTION_DCT_INTERLEAVE TRUE
847 #undef OPTION_NODE_INTERLEAVE
848 #define OPTION_NODE_INTERLEAVE TRUE
849 #undef OPTION_MEM_RESTORE
850 #define OPTION_MEM_RESTORE TRUE
851 #undef OPTION_DIMM_EXCLUDE
852 #define OPTION_DIMM_EXCLUDE TRUE
853 #endif
854#endif
855
856#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
857 #if (OPTION_FAMILY10H == TRUE)
858 #undef OPTION_FAMILY10H_BL
859 #define OPTION_FAMILY10H_BL TRUE
860 #undef OPTION_FAMILY10H_DA
861 #define OPTION_FAMILY10H_DA TRUE
862 #undef OPTION_MEMCTLR_Ni
863 #define OPTION_MEMCTLR_Ni TRUE
864 #undef OPTION_HW_WRITE_LEV_TRAINING
865 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
866 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
867 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
868 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
869 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
870 #undef OPTION_MAX_RD_LAT_TRAINING
871 #define OPTION_MAX_RD_LAT_TRAINING TRUE
872 #undef OPTION_SW_DRAM_INIT
873 #define OPTION_SW_DRAM_INIT TRUE
874 #undef OPTION_S3_MEM_SUPPORT
875 #define OPTION_S3_MEM_SUPPORT TRUE
876 #undef OPTION_CPU_CORELEVLING
877 #define OPTION_CPU_CORELEVLING TRUE
878 #undef OPTION_CPU_CFOH
879 #define OPTION_CPU_CFOH TRUE
880 #undef OPTION_UDIMMS
881 #define OPTION_UDIMMS TRUE
882 #undef OPTION_SODIMMS
883 #define OPTION_SODIMMS TRUE
884 #undef OPTION_DDR3
885 #define OPTION_DDR3 TRUE
886 #undef OPTION_ECC
887 #define OPTION_ECC TRUE
888 #undef OPTION_BANK_INTERLEAVE
889 #define OPTION_BANK_INTERLEAVE TRUE
890 #undef OPTION_DCT_INTERLEAVE
891 #define OPTION_DCT_INTERLEAVE TRUE
892 #undef OPTION_NODE_INTERLEAVE
893 #define OPTION_NODE_INTERLEAVE TRUE
894 #undef OPTION_MEM_RESTORE
895 #define OPTION_MEM_RESTORE TRUE
896 #undef OPTION_DIMM_EXCLUDE
897 #define OPTION_DIMM_EXCLUDE TRUE
898 #endif
899#endif
900
901#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
902 #if (OPTION_FAMILY10H == TRUE)
903 #undef OPTION_FAMILY10H_BL
904 #define OPTION_FAMILY10H_BL TRUE
905 #undef OPTION_FAMILY10H_DA
906 #define OPTION_FAMILY10H_DA TRUE
907 #undef OPTION_FAMILY10H_PH
908 #define OPTION_FAMILY10H_PH TRUE
909 #undef OPTION_FAMILY10H_RB
910 #define OPTION_FAMILY10H_RB TRUE
911 #undef OPTION_MEMCTLR_RB
912 #define OPTION_MEMCTLR_RB TRUE
913 #undef OPTION_MEMCTLR_DA
914 #define OPTION_MEMCTLR_DA TRUE
915 #undef OPTION_MEMCTLR_PH
916 #define OPTION_MEMCTLR_PH TRUE
917 #undef OPTION_HW_WRITE_LEV_TRAINING
918 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
919 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
920 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
921 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
922 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
923 #undef OPTION_MAX_RD_LAT_TRAINING
924 #define OPTION_MAX_RD_LAT_TRAINING TRUE
925 #undef OPTION_SW_DRAM_INIT
926 #define OPTION_SW_DRAM_INIT TRUE
927 #undef OPTION_S3_MEM_SUPPORT
928 #define OPTION_S3_MEM_SUPPORT TRUE
929 #undef OPTION_CPU_CORELEVLING
930 #define OPTION_CPU_CORELEVLING TRUE
931 #undef OPTION_CPU_CFOH
932 #define OPTION_CPU_CFOH TRUE
933 #undef OPTION_IO_CSTATE
934 #define OPTION_IO_CSTATE TRUE
935 #undef OPTION_CPB
936 #define OPTION_CPB TRUE
937 #undef OPTION_UDIMMS
938 #define OPTION_UDIMMS TRUE
939 #undef OPTION_SODIMMS
940 #define OPTION_SODIMMS TRUE
941 #undef OPTION_DDR3
942 #define OPTION_DDR3 TRUE
943 #undef OPTION_ECC
944 #define OPTION_ECC TRUE
945 #undef OPTION_BANK_INTERLEAVE
946 #define OPTION_BANK_INTERLEAVE TRUE
947 #undef OPTION_DCT_INTERLEAVE
948 #define OPTION_DCT_INTERLEAVE TRUE
949 #undef OPTION_NODE_INTERLEAVE
950 #define OPTION_NODE_INTERLEAVE TRUE
951 #undef OPTION_PARALLEL_TRAINING
952 #define OPTION_PARALLEL_TRAINING TRUE
953 #undef OPTION_MEM_RESTORE
954 #define OPTION_MEM_RESTORE TRUE
955 #undef OPTION_ONLINE_SPARE
956 #define OPTION_ONLINE_SPARE TRUE
957 #undef OPTION_DIMM_EXCLUDE
958 #define OPTION_DIMM_EXCLUDE TRUE
959 #endif
960 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
961 #undef OPTION_FAMILY15H_OR
962 #define OPTION_FAMILY15H_OR TRUE
963 #undef OPTION_MEMCTLR_OR
964 #define OPTION_MEMCTLR_OR TRUE
965 #undef OPTION_HW_WRITE_LEV_TRAINING
966 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
967 #undef OPTION_CONTINOUS_PATTERN_GENERATION
968 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
969 #undef OPTION_HW_DQS_REC_EN_TRAINING
970 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
971 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
972 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
973 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
974 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
975 #undef OPTION_MAX_RD_LAT_TRAINING
976 #define OPTION_MAX_RD_LAT_TRAINING TRUE
977 #undef OPTION_SW_DRAM_INIT
978 #define OPTION_SW_DRAM_INIT TRUE
979 #undef OPTION_C6_STATE
980 #define OPTION_C6_STATE TRUE
981 #undef OPTION_IO_CSTATE
982 #define OPTION_IO_CSTATE TRUE
983 #undef OPTION_CPB
984 #define OPTION_CPB TRUE
985 #undef OPTION_CPU_APM
986 #define OPTION_CPU_APM TRUE
987 #undef OPTION_S3_MEM_SUPPORT
988 #define OPTION_S3_MEM_SUPPORT TRUE
989 #undef OPTION_ADDR_TO_CS_TRANSLATOR
990 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
991 #undef OPTION_ATM_MODE
992 #define OPTION_ATM_MODE TRUE
993 #undef OPTION_CPU_CORELEVLING
994 #define OPTION_CPU_CORELEVLING TRUE
995 #undef OPTION_CPU_CFOH
996 #define OPTION_CPU_CFOH TRUE
997 #undef OPTION_MSG_BASED_C1E
998 #define OPTION_MSG_BASED_C1E TRUE
999 #undef OPTION_UDIMMS
1000 #define OPTION_UDIMMS TRUE
1001 #undef OPTION_RDIMMS
1002 #define OPTION_RDIMMS TRUE
1003 #undef OPTION_LRDIMMS
1004 #define OPTION_LRDIMMS TRUE
1005 #undef OPTION_SODIMMS
1006 #define OPTION_SODIMMS TRUE
1007 #undef OPTION_DDR3
1008 #define OPTION_DDR3 TRUE
1009 #undef OPTION_ECC
1010 #define OPTION_ECC TRUE
1011 #undef OPTION_BANK_INTERLEAVE
1012 #define OPTION_BANK_INTERLEAVE TRUE
1013 #undef OPTION_DCT_INTERLEAVE
1014 #define OPTION_DCT_INTERLEAVE TRUE
1015 #undef OPTION_NODE_INTERLEAVE
1016 #define OPTION_NODE_INTERLEAVE TRUE
1017 #undef OPTION_MEM_RESTORE
1018 #define OPTION_MEM_RESTORE TRUE
1019 #undef OPTION_ONLINE_SPARE
1020 #define OPTION_ONLINE_SPARE TRUE
1021 #undef OPTION_DIMM_EXCLUDE
1022 #define OPTION_DIMM_EXCLUDE TRUE
1023 #endif
1024#endif
1025
1026#define OPTION_ACPI_PSTATES TRUE
1027#define OPTION_WHEA TRUE
1028#define OPTION_DMI TRUE
1029#define OPTION_EARLY_SAMPLES FALSE
1030#define CFG_ACPI_PSTATES_PPC TRUE
1031#define CFG_ACPI_PSTATES_PCT TRUE
1032#define CFG_ACPI_PSTATES_PSD TRUE
1033#define CFG_ACPI_PSTATES_PSS TRUE
1034#define CFG_ACPI_PSTATES_XPSS TRUE
1035#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
1036#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
1037#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
1038#define OPTION_ALIB TRUE
1039/*---------------------------------------------------------------------------
1040 * Processing the options: Second, process the user's selections
1041 *--------------------------------------------------------------------------*/
1042#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
1043 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
1044 #undef OPTION_MULTISOCKET
1045 #define OPTION_MULTISOCKET FALSE
1046 #endif
1047#endif
1048#ifdef BLDOPT_REMOVE_ECC_SUPPORT
1049 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
1050 #undef OPTION_ECC
1051 #define OPTION_ECC FALSE
1052 #endif
1053#endif
1054#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
1055 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
1056 #undef OPTION_UDIMMS
1057 #define OPTION_UDIMMS FALSE
1058 #endif
1059#endif
1060#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
1061 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
1062 #undef OPTION_RDIMMS
1063 #define OPTION_RDIMMS FALSE
1064 #endif
1065#endif
1066#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
1067 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
1068 #undef OPTION_SODIMMS
1069 #define OPTION_SODIMMS FALSE
1070 #endif
1071#endif
1072#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
1073 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1074 #undef OPTION_LRDIMMS
1075 #define OPTION_LRDIMMS FALSE
1076 #endif
1077#endif
1078#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
1079 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
1080 #undef OPTION_BANK_INTERLEAVE
1081 #define OPTION_BANK_INTERLEAVE FALSE
1082 #endif
1083#endif
1084#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
1085 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
1086 #undef OPTION_DCT_INTERLEAVE
1087 #define OPTION_DCT_INTERLEAVE FALSE
1088 #endif
1089#endif
1090#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
1091 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
1092 #undef OPTION_NODE_INTERLEAVE
1093 #define OPTION_NODE_INTERLEAVE FALSE
1094 #endif
1095#endif
1096#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
1097 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
1098 #undef OPTION_PARALLEL_TRAINING
1099 #define OPTION_PARALLEL_TRAINING FALSE
1100 #endif
1101#endif
1102#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
1103 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
1104 #undef OPTION_ONLINE_SPARE
1105 #define OPTION_ONLINE_SPARE FALSE
1106 #endif
1107#endif
1108#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
1109 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
1110 #undef OPTION_MEM_RESTORE
1111 #define OPTION_MEM_RESTORE FALSE
1112 #endif
1113#endif
1114#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
1115 #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
1116 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1117 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
1118 #endif
1119#endif
1120#ifdef BLDOPT_REMOVE_ACPI_PSTATES
1121 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
1122 #undef OPTION_ACPI_PSTATES
1123 #define OPTION_ACPI_PSTATES FALSE
1124 #endif
1125#endif
1126#ifdef BLDOPT_REMOVE_SRAT
1127 #if BLDOPT_REMOVE_SRAT == TRUE
1128 #undef OPTION_SRAT
1129 #define OPTION_SRAT FALSE
1130 #endif
1131#endif
1132#ifdef BLDOPT_REMOVE_SLIT
1133 #if BLDOPT_REMOVE_SLIT == TRUE
1134 #undef OPTION_SLIT
1135 #define OPTION_SLIT FALSE
1136 #endif
1137#endif
1138#ifdef BLDOPT_REMOVE_WHEA
1139 #if BLDOPT_REMOVE_WHEA == TRUE
1140 #undef OPTION_WHEA
1141 #define OPTION_WHEA FALSE
1142 #endif
1143#endif
1144#ifdef BLDOPT_REMOVE_DMI
1145 #if BLDOPT_REMOVE_DMI == TRUE
1146 #undef OPTION_DMI
1147 #define OPTION_DMI FALSE
1148 #endif
1149#endif
1150#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
1151 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
1152 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1153 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
1154 #endif
1155#endif
1156
1157#ifdef BLDOPT_REMOVE_HT_ASSIST
1158 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
1159 #undef OPTION_HT_ASSIST
1160 #define OPTION_HT_ASSIST FALSE
1161 #endif
1162#endif
1163
1164#ifdef BLDOPT_REMOVE_ATM_MODE
1165 #if BLDOPT_REMOVE_ATM_MODE == TRUE
1166 #undef OPTION_ATM_MODE
1167 #define OPTION_ATM_MODE FALSE
1168 #endif
1169#endif
1170
1171#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
1172 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
1173 #undef OPTION_MSG_BASED_C1E
1174 #define OPTION_MSG_BASED_C1E FALSE
1175 #endif
1176#endif
1177
1178#ifdef BLDOPT_REMOVE_C6_STATE
1179 #if BLDOPT_REMOVE_C6_STATE == TRUE
1180 #undef OPTION_C6_STATE
1181 #define OPTION_C6_STATE FALSE
1182 #endif
1183#endif
1184
1185#ifdef BLDOPT_REMOVE_GFX_RECOVERY
1186 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
1187 #undef OPTION_GFX_RECOVERY
1188 #define OPTION_GFX_RECOVERY FALSE
1189 #endif
1190#endif
1191
1192#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
1193 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
1194 #undef CFG_ACPI_PSTATES_PPC
1195 #define CFG_ACPI_PSTATES_PPC FALSE
1196 #endif
1197#endif
1198
1199#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
1200 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
1201 #undef CFG_ACPI_PSTATES_PCT
1202 #define CFG_ACPI_PSTATES_PCT FALSE
1203 #endif
1204#endif
1205
1206#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
1207 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
1208 #undef CFG_ACPI_PSTATES_PSD
1209 #define CFG_ACPI_PSTATES_PSD FALSE
1210 #endif
1211#endif
1212
1213#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
1214 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
1215 #undef CFG_ACPI_PSTATES_PSS
1216 #define CFG_ACPI_PSTATES_PSS FALSE
1217 #endif
1218#endif
1219
1220#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
1221 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
1222 #undef CFG_ACPI_PSTATES_XPSS
1223 #define CFG_ACPI_PSTATES_XPSS FALSE
1224 #endif
1225#endif
1226
1227#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
1228 #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE
1229 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
1230 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
1231 #endif
1232#endif
1233
1234#ifdef BLDCFG_PSTATE_HPC_MODE
1235 #if BLDCFG_PSTATE_HPC_MODE == TRUE
1236 #undef OPTION_CPU_PSTATE_HPC_MODE
1237 #define OPTION_CPU_PSTATE_HPC_MODE TRUE
1238 #endif
1239#endif
1240
1241#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
1242 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
1243 #undef CFG_ACPI_PSTATE_PSD_INDPX
1244 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
1245 #endif
1246#endif
1247
1248#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
1249 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
1250 #undef CFG_VRM_HIGH_SPEED_ENABLE
1251 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
1252 #endif
1253#endif
1254
1255#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
1256 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
1257 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
1258 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
1259 #endif
1260#endif
1261
1262#ifdef BLDCFG_STARTING_BUSNUM
1263 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
1264#else
1265 #define CFG_STARTING_BUSNUM (0)
1266#endif
1267
1268#ifdef BLDCFG_AMD_PLATFORM_TYPE
1269 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
1270#else
1271 #define CFG_AMD_PLATFORM_TYPE 0
1272#endif
1273
1274CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
1275
1276#ifdef BLDCFG_MAXIMUM_BUSNUM
1277 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
1278#else
1279 #define CFG_MAXIMUM_BUSNUM (0xF8)
1280#endif
1281
1282#ifdef BLDCFG_ALLOCATED_BUSNUM
1283 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
1284#else
1285 #define CFG_ALLOCATED_BUSNUM (0x20)
1286#endif
1287
1288#ifdef BLDCFG_BUID_SWAP_LIST
1289 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
1290#else
1291 #define CFG_BUID_SWAP_LIST (NULL)
1292#endif
1293
1294#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
1295 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
1296#else
1297 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
1298#endif
1299
1300#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
1301 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
1302#else
1303 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
1304#endif
1305
1306#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
1307 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
1308#else
1309 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
1310#endif
1311
1312#ifdef BLDCFG_BUS_NUMBERS_LIST
1313 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
1314#else
1315 #define CFG_BUS_NUMBERS_LIST (NULL)
1316#endif
1317
1318#ifdef BLDCFG_IGNORE_LINK_LIST
1319 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
1320#else
1321 #define CFG_IGNORE_LINK_LIST (NULL)
1322#endif
1323
1324#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
1325 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
1326#else
1327 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
1328#endif
1329
1330#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
1331 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
1332#else
1333 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
1334#endif
1335
1336#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
1337 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
1338#else
1339 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
1340#endif
1341
1342#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
1343 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
1344#else
1345 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
1346#endif
1347
1348#ifdef BLDCFG_USE_HT_ASSIST
1349 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
1350#else
1351 #define CFG_USE_HT_ASSIST (TRUE)
1352#endif
1353
1354#ifdef BLDCFG_USE_ATM_MODE
1355 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
1356#else
1357 #define CFG_USE_ATM_MODE (TRUE)
1358#endif
1359
1360#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
1361 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
1362#else
1363 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
1364#endif
1365
1366#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
1367 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
1368#else
1369 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO)
1370#endif
1371
1372#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
1373 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
1374#else
1375 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO)
1376#endif
1377
1378#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
1379 #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
1380#else
1381 #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO)
1382#endif
1383
1384#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
1385 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
1386#else
1387 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
1388#endif
1389
1390#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
1391 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
1392#else
1393 #define CFG_VRM_ADDITIONAL_DELAY (0)
1394#endif
1395
1396#ifdef BLDCFG_VRM_CURRENT_LIMIT
1397 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
1398#else
1399 #define CFG_VRM_CURRENT_LIMIT 0
1400#endif
1401
1402#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
1403 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
1404#else
1405 #define CFG_VRM_LOW_POWER_THRESHOLD 0
1406#endif
1407
1408#ifdef BLDCFG_VRM_SLEW_RATE
1409 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
1410#else
1411 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
1412#endif
1413
1414#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1415 #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1416#else
1417 #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
1418#endif
1419
1420#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
1421 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
1422#else
1423 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
1424#endif
1425
1426#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
1427 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
1428#else
1429 #define CFG_VRM_NB_CURRENT_LIMIT (0)
1430#endif
1431
1432#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1433 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1434#else
1435 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
1436#endif
1437
1438#ifdef BLDCFG_VRM_NB_SLEW_RATE
1439 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
1440#else
1441 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
1442#endif
1443
1444#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1445 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1446#else
1447 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
1448#endif
1449
1450
1451#ifdef BLDCFG_PLAT_NUM_IO_APICS
1452 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
1453#else
1454 #define CFG_PLAT_NUM_IO_APICS 0
1455#endif
1456
1457#ifdef BLDCFG_MEM_INIT_PSTATE
1458 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
1459#else
1460 #define CFG_MEM_INIT_PSTATE 0
1461#endif
1462
1463#ifdef BLDCFG_PLATFORM_C1E_MODE
1464 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
1465#else
1466 #define CFG_C1E_MODE C1eModeDisabled
1467#endif
1468
1469#ifdef BLDCFG_PLATFORM_C1E_OPDATA
1470 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
1471#else
1472 #define CFG_C1E_OPDATA 0
1473#endif
1474
1475#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
1476 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
1477#else
1478 #define CFG_C1E_OPDATA1 0
1479#endif
1480
1481#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
1482 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
1483#else
1484 #define CFG_C1E_OPDATA2 0
1485#endif
1486
1487#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
1488 #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3
1489#else
1490 #define CFG_C1E_OPDATA3 0
1491#endif
1492
1493#ifdef BLDCFG_PLATFORM_CSTATE_MODE
1494 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
1495#else
1496 #define CFG_CSTATE_MODE CStateModeDisabled
1497#endif
1498
1499#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
1500 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
1501#else
1502 #define CFG_CSTATE_OPDATA 0
1503#endif
1504
1505#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1506 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1507#else
1508 #define CFG_CSTATE_IO_BASE_ADDRESS 0
1509#endif
1510
1511#ifdef BLDCFG_PLATFORM_CPB_MODE
1512 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
1513#else
1514 #define CFG_CPB_MODE CpbModeAuto
1515#endif
1516
1517#ifdef BLDCFG_CORE_LEVELING_MODE
1518 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
1519#else
1520 #define CFG_CORE_LEVELING_MODE 0
1521#endif
1522
1523#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
1524 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
1525#else
1526 #define CFG_AMD_PSTATE_CAP_VALUE 0
1527#endif
1528
1529#ifdef BLDCFG_HEAP_DRAM_ADDRESS
1530 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
1531#else
1532 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
1533#endif
1534
1535#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1536 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1537#else
1538 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
1539#endif
1540
1541#ifdef BLDCFG_MEMORY_MODE_UNGANGED
1542 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
1543#else
1544 #define CFG_MEMORY_MODE_UNGANGED TRUE
1545#endif
1546
1547#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1548 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1549#else
1550 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
1551#endif
1552
1553#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
1554 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
1555#else
1556 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
1557#endif
1558
1559#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
1560 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
1561#else
1562 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
1563#endif
1564
1565#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
1566 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
1567#else
1568 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
1569#endif
1570
1571#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
1572 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
1573#else
1574 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
1575#endif
1576
1577#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
1578 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
1579#else
1580 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
1581#endif
1582
1583#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1584 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1585#else
1586 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
1587#endif
1588
1589#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1590 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1591#else
1592 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
1593#endif
1594
1595#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1596 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1597#else
1598 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
1599#endif
1600
1601#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1602 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1603#else
1604 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
1605#endif
1606
1607#ifdef BLDCFG_MEMORY_POWER_DOWN
1608 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
1609#else
1610 #define CFG_MEMORY_POWER_DOWN FALSE
1611#endif
1612
1613#ifdef BLDCFG_POWER_DOWN_MODE
1614 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
1615#else
1616 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
1617#endif
1618
1619#ifdef BLDCFG_ONLINE_SPARE
1620 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
1621#else
1622 #define CFG_ONLINE_SPARE FALSE
1623#endif
1624
1625#ifdef BLDCFG_MEMORY_PARITY_ENABLE
1626 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
1627#else
1628 #define CFG_MEMORY_PARITY_ENABLE FALSE
1629#endif
1630
1631#ifdef BLDCFG_BANK_SWIZZLE
1632 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
1633#else
1634 #define CFG_BANK_SWIZZLE TRUE
1635#endif
1636
1637#ifdef BLDCFG_TIMING_MODE_SELECT
1638 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1639#else
1640 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1641#endif
1642
1643#ifdef BLDCFG_MEMORY_CLOCK_SELECT
1644 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1645#else
1646 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
1647#endif
1648
1649#ifdef BLDCFG_DQS_TRAINING_CONTROL
1650 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1651#else
1652 #define CFG_DQS_TRAINING_CONTROL TRUE
1653#endif
1654
1655#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1656 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1657#else
1658 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1659#endif
1660
1661#ifdef BLDCFG_USE_BURST_MODE
1662 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1663#else
1664 #define CFG_USE_BURST_MODE FALSE
1665#endif
1666
1667#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1668 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1669#else
1670 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1671#endif
1672
1673#ifdef BLDCFG_ENABLE_ECC_FEATURE
1674 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1675#else
1676 #define CFG_ENABLE_ECC_FEATURE TRUE
1677#endif
1678
1679#ifdef BLDCFG_ECC_REDIRECTION
1680 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1681#else
1682 #define CFG_ECC_REDIRECTION FALSE
1683#endif
1684
1685#ifdef BLDCFG_SCRUB_DRAM_RATE
1686 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1687#else
1688 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
1689#endif
1690
1691#ifdef BLDCFG_SCRUB_L2_RATE
1692 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1693#else
1694 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
1695#endif
1696
1697#ifdef BLDCFG_SCRUB_L3_RATE
1698 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1699#else
1700 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
1701#endif
1702
1703#ifdef BLDCFG_SCRUB_IC_RATE
1704 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1705#else
1706 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
1707#endif
1708
1709#ifdef BLDCFG_SCRUB_DC_RATE
1710 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1711#else
1712 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
1713#endif
1714
1715#ifdef BLDCFG_ECC_SYNC_FLOOD
1716 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1717#else
1718 #define CFG_ECC_SYNC_FLOOD TRUE
1719#endif
1720
1721#ifdef BLDCFG_ECC_SYMBOL_SIZE
1722 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1723#else
1724 #define CFG_ECC_SYMBOL_SIZE 0
1725#endif
1726
1727#ifdef BLDCFG_1GB_ALIGN
1728 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1729#else
1730 #define CFG_1GB_ALIGN FALSE
1731#endif
1732
1733#ifdef BLDCFG_UMA_ALLOCATION_MODE
1734 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1735#else
1736 #define CFG_UMA_MODE UMA_AUTO
1737#endif
1738
1739#ifdef BLDCFG_FORCE_TRAINING_MODE
1740 #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE
1741#else
1742 #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO
1743#endif
1744
1745#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1746 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1747#else
1748 #define CFG_UMA_SIZE 0
1749#endif
1750
1751#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1752 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1753#else
1754 #define CFG_UMA_ABOVE4G FALSE
1755#endif
1756
1757#ifdef BLDCFG_UMA_ALIGNMENT
1758 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1759#else
1760 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1761#endif
1762
1763#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1764 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1765#else
1766 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1767#endif
1768
1769#ifdef BLDCFG_S3_LATE_RESTORE
1770 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1771#else
1772 #define CFG_S3_LATE_RESTORE TRUE
1773#endif
1774
1775#ifdef BLDCFG_USE_32_BYTE_REFRESH
1776 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1777#else
1778 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1779#endif
1780
1781#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1782 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1783#else
1784 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1785#endif
1786
1787#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1788 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1789#else
1790 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1791#endif
1792
1793#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1794 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1795#else
1796 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1797#endif
1798
1799#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1800 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1801#else
1802 #define CFG_GNB_HD_AUDIO TRUE
1803#endif
1804
1805#ifdef BLDCFG_CFG_ABM_SUPPORT
1806 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1807#else
1808 #define CFG_ABM_SUPPORT FALSE
1809#endif
1810
1811#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1812 #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1813#else
1814 #define CFG_DYNAMIC_REFRESH_RATE 0
1815#endif
1816
1817#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1818 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1819#else
1820 #define CFG_LCD_BACK_LIGHT_CONTROL 0
1821#endif
1822
1823#ifdef BLDCFG_STEREO_3D_PINOUT
1824 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1825#else
1826 #define CFG_GNB_STEREO_3D_PINOUT 0
1827#endif
1828
1829#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
1830 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT
1831#else
1832 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE
1833#endif
1834
1835#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1836 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1837#else
1838 #define CFG_GNB_IGPU_SSID 0
1839#endif
1840
1841#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1842 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1843#else
1844 #define CFG_GNB_HDAUDIO_SSID 0
1845#endif
1846
1847#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1848 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1849#else
1850 #define CFG_GNB_PCIE_SSID 0x12341022
1851#endif
1852
1853#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1854 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1855#else
1856 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1857#endif
1858
1859#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1860 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1861#else
1862 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1863#endif
1864
1865#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1866 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1867#else
1868 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1869#endif
1870
1871#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1872 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1873#else
1874 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
1875#endif
1876
1877#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1878 #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1879#else
1880 #define CFG_ENABLE_EXTERNAL_VREF FALSE
1881#endif
1882
1883#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1884 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1885 #undef OPTION_EARLY_SAMPLES
1886 #define OPTION_EARLY_SAMPLES FALSE
1887 #else
1888 #undef OPTION_EARLY_SAMPLES
1889 #define OPTION_EARLY_SAMPLES TRUE
1890 #endif
1891#endif
1892
1893#ifdef BLDOPT_REMOVE_ALIB
1894 #if BLDOPT_REMOVE_ALIB == TRUE
1895 #undef OPTION_ALIB
1896 #define OPTION_ALIB FALSE
1897 #else
1898 #undef OPTION_ALIB
1899 #define OPTION_ALIB TRUE
1900 #endif
1901#endif
1902
1903#ifdef BLDOPT_REMOVE_FCH_COMPONENT
1904 #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
1905 #undef FCH_SUPPORT
1906 #define FCH_SUPPORT FALSE
1907 #endif
1908#endif
1909
1910#ifdef BLDCFG_IOMMU_SUPPORT
1911 #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT
1912#else
1913 #define CFG_IOMMU_SUPPORT TRUE
1914#endif
1915
1916#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1917 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1918#else
1919 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0
1920#endif
1921
1922#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1923 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1924#else
1925 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0
1926#endif
1927
1928#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1929 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1930#else
1931 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0
1932#endif
1933
1934#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1935 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1936#else
1937 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0
1938#endif
1939
1940#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1941 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1942#else
1943 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0
1944#endif
1945
1946#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1947 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1948#else
1949 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
1950#endif
1951
1952#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1953 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1954#else
1955 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
1956#endif
1957
1958#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1959 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1960#else
1961 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0
1962#endif
1963
1964#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1965 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1966#else
1967 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0
1968#endif
1969
1970
1971// BLDCFG_LVDS_24BBP_PANEL_MODE
1972// This specifies the LVDS 24 BBP mode.
1973// 0 - Use LDI mode (default).
1974// 1 - Use FPDI mode.
1975#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
1976 #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE
1977#else
1978 #define CFG_LVDS_24BBP_PANEL_MODE 0
1979#endif
1980
1981#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1982 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1983#else
1984 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1985#endif
1986
1987#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1988 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1989#else
1990 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1991#endif
1992
1993#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1994 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1995#else
1996 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1997#endif
1998
1999#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
2000 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
2001#else
2002 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
2003#endif
2004
2005#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
2006 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
2007#else
2008 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
2009#endif
2010
2011#ifdef BLDCFG_FORCE_MICROSERVER
2012 #define CFG_FORCE_MICROSERVER BLDCFG_FORCE_MICROSERVER
2013#else
2014 #define CFG_FORCE_MICROSERVER FALSE
2015#endif
2016
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]2017#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
2018 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
2019#else
2020 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
2021#endif
2022
2023#ifdef BLDCFG_PCI_MMIO_BASE
2024 #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
2025#else
2026 #define CFG_PCI_MMIO_BASE (0)
2027#endif
2028
2029#ifdef BLDCFG_PCI_MMIO_SIZE
2030 #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
2031#else
2032 #define CFG_PCI_MMIO_SIZE (0)
2033#endif
2034
2035#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
2036 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
2037#else
2038 #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
2039#endif
2040
2041#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
2042 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
2043#else
2044 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
2045#endif
2046
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]2047/*---------------------------------------------------------------------------
2048 * Processing the options: Third, perform the option cross checks
2049 *--------------------------------------------------------------------------*/
2050// Assure that at least one type of memory support is included
2051#if OPTION_UDIMMS == FALSE
2052 #if OPTION_RDIMMS == FALSE
2053 #if OPTION_SODIMMS == FALSE
2054 #if OPTION_LRDIMMS == FALSE
2055 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
2056 #endif
2057 #endif
2058 #endif
2059#endif
2060// Ensure at least one dimm type is capable
2061#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
2062 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
2063 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
2064 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2065 #error BLDCFG: No dimm type is capable
2066 #endif
2067 #endif
2068 #endif
2069#endif
2070// Check LRDIMM CODE and LRDIMM CFG item
2071#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2072 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
2073 #error Warning: LRDIMM capability is false, but LRIDMM support code included
2074 #endif
2075#endif
2076// Turn off multi-socket based features if only one node...
2077#if OPTION_MULTISOCKET == FALSE
2078 #undef OPTION_PARALLEL_TRAINING
2079 #define OPTION_PARALLEL_TRAINING FALSE
2080 #undef OPTION_NODE_INTERLEAVE
2081 #define OPTION_NODE_INTERLEAVE FALSE
2082#endif
2083// Ensure that at least one write leveling option is selected
2084#if OPTION_DDR3 == TRUE
2085 #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
2086 #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
2087 #error No Write leveling option selected for DDR3
2088 #endif
2089 #endif
2090 #if OPTION_SW_DRAM_INIT == FALSE
2091 #error Software dram init must be enabled for DDR3 dimms
2092 #endif
2093#endif
2094// Ensure at least one DQS receiver training option is selected
2095#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
2096 #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2097 #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2098 #error No DQS receiver training option has been slected
2099 #endif
2100 #endif
2101#endif
2102// Ensure at least one Rd Wr position training option has been selected
2103#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
2104 #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
2105 #error No Rd Wr position training option has been selected
2106 #endif
2107#endif
2108// Ensure at least one dram init option has been selected
2109#if OPTION_HW_DRAM_INIT == FALSE
2110 #if OPTION_SW_DRAM_INIT == FALSE
2111 #error No Dram init option has been selected
2112 #endif
2113#endif
2114// Ensure the frequency limit is valid
2115#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
2116 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
2117 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
2118 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
2119 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
2120 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
2121 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
2122 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
2123 #error BLDCFG: Unsupported memory bus frequency
2124 #endif
2125 #endif
2126 #endif
2127 #endif
2128 #endif
2129 #endif
2130 #endif
2131#endif
2132// Ensure timing mode is valid
2133#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
2134 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
2135 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
2136 #error BLDCFG: Invalid timing mode is set
2137 #endif
2138 #endif
2139#endif
2140// Ensure the scrub rate is valid
2141#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
2142 #error BLDCFG: Unsupported dram scrub rate set
2143#endif
2144#if CFG_SCRUB_L2_RATE > 0x16
2145 #error BLDCFG: Unsupported L2 scrubber rate set
2146#endif
2147#if CFG_SCRUB_L3_RATE > 0x16
2148 #error BLDCFG: unsupported L3 scrubber rate set
2149#endif
2150#if CFG_SCRUB_IC_RATE > 0x16
2151 #error BLDCFG: Unsupported Instruction cache scrub rate set
2152#endif
2153#if CFG_SCRUB_DC_RATE > 0x16
2154 #error BLDCFG: Unsupported Dcache scrub rate set
2155#endif
2156// Ensure Quad rank dimm type is valid
2157#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
2158 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
2159 #error BLDCFG: Invalid quad rank dimm type set
2160 #endif
2161#endif
2162// Ensure ECC symbol size is valid
2163#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
2164 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
2165 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
2166 #error BLDCFG: Invalid Ecc symbol size set
2167 #endif
2168 #endif
2169#endif
2170// Ensure power down mode is valid
2171#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
2172 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
2173 #error BLDCFG: Invalid power down mode set
2174 #endif
2175#endif
2176
2177/*****************************************************************************
2178 *
2179 * Process the option logic, setting local control variables
2180 *
2181 ****************************************************************************/
2182#if OPTION_ACPI_PSTATES == TRUE
2183 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
2184 #define OPTFCN_GATHER_DATA PStateGatherData
2185 #if OPTION_MULTISOCKET == TRUE
2186 #define OPTFCN_PSTATE_LEVELING PStateLeveling
2187 #else
2188 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2189 #endif
2190#else
2191 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
2192 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
2193 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2194#endif
2195
2196
2197/*****************************************************************************
2198 *
2199 * Include the structure definitions for the defaults table structures
2200 *
2201 ****************************************************************************/
Kyösti Mälkki062ef1c2016-04-19 15:18:02 +0300[diff] [blame^]2202#include <CommonReturns.h>
2203#include <agesa-entry-cfg.h>
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]2204#include "Options.h"
2205#include "OptionCpuFamiliesInstall.h"
2206#include "OptionsHt.h"
2207#include "OptionHtInstall.h"
2208#include "OptionMemory.h"
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]2209#include "OptionMemoryInstall.h"
2210#include "OptionMemoryRecovery.h"
2211#include "OptionMemoryRecoveryInstall.h"
2212#include "OptionCpuFeaturesInstall.h"
2213#include "OptionDmi.h"
2214#include "OptionDmiInstall.h"
2215#include "OptionPstate.h"
2216#include "OptionPstateInstall.h"
2217#include "OptionWhea.h"
2218#include "OptionWheaInstall.h"
2219#include "OptionSrat.h"
2220#include "OptionSratInstall.h"
2221#include "OptionSlit.h"
2222#include "OptionSlitInstall.h"
2223#include "OptionMultiSocket.h"
2224#include "OptionMultiSocketInstall.h"
2225#include "OptionIdsInstall.h"
2226#include "OptionGfxRecovery.h"
2227#include "OptionGfxRecoveryInstall.h"
2228#include "OptionGnb.h"
2229#include "OptionGnbInstall.h"
2230#include "OptionS3ScriptInstall.h"
2231#include "OptionFchInstall.h"
2232
2233
2234/*****************************************************************************
2235 *
2236 * Generate the output structures (defaults tables)
2237 *
2238 ****************************************************************************/
2239
2240FCH_PLATFORM_POLICY FchUserOptions = {
2241 CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress
2242 CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress
2243 CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress
2244 CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr
2245 CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr
2246 CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr
2247 CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr
2248 CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr
2249 CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr
2250 CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr
2251 CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase
2252 CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase
2253 CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress
2254 CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress
2255 CFG_AZALIA_SSID, // CfgAzaliaSsid
2256 CFG_SMBUS_SSID, // CfgSmbusSsid
2257 CFG_IDE_SSID, // CfgIdeSsid
2258 CFG_SATA_AHCI_SSID, // CfgSataAhciSsid
2259 CFG_SATA_IDE_SSID, // CfgSataIdeSsid
2260 CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid
2261 CFG_SATA_RAID_SSID, // CfgSataRaidSsid
2262 CFG_EHCI_SSID, // CfgEhcidSsid
2263 CFG_OHCI_SSID, // CfgOhcidSsid
2264 CFG_LPC_SSID, // CfgLpcSsid
2265 CFG_SD_SSID, // CfgSdSsid
2266 CFG_XHCI_SSID, // CfgXhciSsid
2267 CFG_FCH_PORT80_BEHIND_PCIB, // CfgFchPort80BehindPcib
2268 CFG_FCH_ENABLE_ACPI_SLEEP_TRAP, // CfgFchEnableAcpiSleepTrap
2269 CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig
2270 CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present
2271 CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present
2272 CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present
2273 CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present
2274 CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug
2275 CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug
2276 CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug
2277 CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug
2278
2279 CFG_FCH_ESATA_PORT_BITMAP, // CfgFchEsataPortBitMap
2280 CFG_FCH_IR_PIN_CONTROL, // CfgFchIrPinControl
2281 CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl
2282 CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl
2283 CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl
2284 CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl
2285};
2286
2287BUILD_OPT_CFG UserOptions = {
2288 { // AGESA version string
2289 AGESA_CODE_SIGNATURE, // code header Signature
2290 AGESA_PACKAGE_STRING, // 8 character ID
2291 AGESA_VERSION_STRING, // 12 character version string
2292 0 // null string terminator
2293 },
2294 //Build Option Area
2295 OPTION_UDIMMS, //UDIMMS
2296 OPTION_RDIMMS, //RDIMMS
2297 OPTION_LRDIMMS, //LRDIMMS
2298 OPTION_ECC, //ECC
2299 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
2300 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
2301 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
2302 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
2303 OPTION_ONLINE_SPARE, //ONLINE_SPARE
2304 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
2305 OPTION_MULTISOCKET, //MULTISOCKET
2306 OPTION_ACPI_PSTATES, //ACPI_PSTATES
2307 OPTION_CPU_PSTATE_HPC_MODE, //High Preformace Computing (HPC) mode
2308 OPTION_SRAT, //SRAT
2309 OPTION_SLIT, //SLIT
2310 OPTION_WHEA, //WHEA
2311 OPTION_DMI, //DMI
2312 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
2313 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
2314
2315 //Build Configuration Area
2316 CFG_PCI_MMIO_BASE,
2317 CFG_PCI_MMIO_SIZE,
2318 {
2319 // CoreVrm
2320 {
2321 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
2322 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
2323 CFG_VRM_SLEW_RATE, // VrmSlewRate
2324 CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay
2325 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
2326 CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
2327 },
2328 // NbVrm
2329 {
2330 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
2331 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
2332 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
2333 CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay
2334 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
2335 CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
2336 }
2337 },
2338 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
2339 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
2340 CFG_C1E_MODE, //C1eMode
2341 CFG_C1E_OPDATA, //C1ePlatformData
2342 CFG_C1E_OPDATA1, //C1ePlatformData1
2343 CFG_C1E_OPDATA2, //C1ePlatformData2
2344 CFG_C1E_OPDATA3, //C1ePlatformData3
2345 CFG_CSTATE_MODE, //CStateMode
2346 CFG_CSTATE_OPDATA, //CStatePlatformData
2347 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
2348 CFG_CPB_MODE, //CpbMode
2349 LOW_POWER_PSTATE_FOR_PROCHOT_AUTO, //Low power Pstate for PROCHOT, it's always set to 'AUTO'
2350 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
2351 {
2352 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
2353 CFG_USE_HT_ASSIST, // CfgUseHtAssist
2354 CFG_USE_ATM_MODE, // CfgUseAtmMode
2355 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
2356 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
2357 // ADVANCED_PERFORMANCE_PROFILE
2358 {
2359 CFG_PERFORMANCE_HARDWARE_PREFETCHER, // Hardware prefetcher mode
2360 CFG_PERFORMANCE_SOFTWARE_PREFETCHES, // Software prefetcher mode
2361 CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode
2362 },
2363 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
2364 },
2365 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
2366 CFG_AMD_PLATFORM_TYPE, //AmdPlatformType
2367 CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck
2368
2369 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
2370 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
2371 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
2372 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
2373 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
2374 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
2375 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
2376 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
2377 CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb
2378 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
2379 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
2380 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
2381 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
2382 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
2383 CFG_ONLINE_SPARE, // CfgOnlineSpare
2384 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
2385 CFG_BANK_SWIZZLE, // CfgBankSwizzle
2386 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
2387 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
2388 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
2389 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
2390 CFG_USE_BURST_MODE, // CfgUseBurstMode
2391 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
2392 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
2393 CFG_ECC_REDIRECTION, // CfgEccRedirection
2394 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
2395 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
2396 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
2397 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
2398 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
2399 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
2400 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
2401 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
2402 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
2403 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
2404 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
2405 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
2406 CFG_UMA_MODE, // CfgUmaMode
2407 CFG_UMA_SIZE, // CfgUmaSize
2408 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
2409 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
2410 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
2411 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
2412 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
2413 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
2414 CFG_ABM_SUPPORT, // CfgAbmSupport
2415 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
2416 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
2417 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
2418 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
2419 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
2420 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
2421 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
2422 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
2423 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
2424
2425 &FchUserOptions, // FchBldCfg
2426
2427 CFG_IOMMU_SUPPORT, // CfgIommuSupport
2428 CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe
2429 CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl
2430 CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon
2431 CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
2432 CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
2433 CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
2434 CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
2435 CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq
2436 CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue
2437 CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode
2438 {{
2439 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
2440 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
2441 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
2442 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
2443 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
2444 }},
2445 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
2446 CFG_ENABLE_EXTERNAL_VREF, // CfgExternalVrefCtlFeature
2447 CFG_FORCE_TRAIN_MODE, // CfgForceTrainMode
2448 CFG_GNB_REMOTE_DISPLAY_SUPPORT, // CfgGnbRemoteDisplaySupport
2449 (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
2450 0, //reserved...
2451};
2452
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]2453CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
2454{
2455 IDS_LATE_RUN_AP_TASK
2456 // Get DMI info
2457 CPU_DMI_AP_GET_TYPE4_TYPE7
2458 // Probe filter enable
2459 L3_FEAT_AP_DISABLE_CACHE
2460 L3_FEAT_AP_ENABLE_CACHE
2461 // Cpu Late Init
2462 CPU_LATE_INIT_AP_TASK
2463 { 0, NULL }
2464};
2465
2466#if AGESA_ENTRY_INIT_EARLY == TRUE
2467 #if IDSOPT_IDS_ENABLED == TRUE
2468 #if IDSOPT_TRACING_ENABLED == TRUE
2469 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
2470 CONST CHAR8 *BldOptDebugOutput[] = {
2471 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
2472 //Build Option Area
2473 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
2474 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
2475 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
2476 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
2477 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
2478 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
2479 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
2480 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
2481 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
2482 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
2483 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
2484 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
2485 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
2486 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
2487 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
2488 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
2489 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
2490 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
2491
2492 //Build Configuration Area
2493 // CoreVrm
2494 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
2495 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
2496 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
2497 MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY)
2498 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
2499 MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
2500 // NbVrm
2501 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
2502 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
2503 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
2504 MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY)
2505 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
2506 MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
2507
2508 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
2509 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
2510 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
2511 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
2512 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
2513 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
2514 MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3)
2515 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
2516 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
2517 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
2518 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
2519 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
2520
2521 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
2522 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
2523 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
2524 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
2525 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2526 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
2527
2528 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
2529
2530 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2531 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2532 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2533 MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE),
2534
2535 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2536 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2537 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2538
2539 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2540 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2541 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2542 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2543 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2544 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2545 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2546 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2547 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2548 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2549 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2550
2551 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2552 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2553 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2554 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2555 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2556 MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
2557 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2558 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2559 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2560
2561 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2562 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2563 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2564 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2565
2566 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2567 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2568 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2569 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2570 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2571 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2572 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2573 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2574 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2575 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2576 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2577
2578 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2579 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2580
2581 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2582
2583 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2584 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2585 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2586 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2587 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2588 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2589 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2590 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2591 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2592 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID)
2593 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID)
2594 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID)
2595 MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT)
2596 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM)
2597 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
2598 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
2599 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
2600 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
2601 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
2602 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
2603 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
2604 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
2605 MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
2606 MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
2607 MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE),
2608 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
2609 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
2610 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
2611 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
2612 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
2613 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
2614 MAKE_DBG_STR (\nCfgExtVref , CFG_ENABLE_EXTERNAL_VREF),
2615 MAKE_DBG_STR (\nCfgForceTrainMode , CFG_FORCE_TRAIN_MODE),
2616 MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport , CFG_GNB_REMOTE_DISPLAY_CONFIG),
2617 MAKE_DBG_STR (\nCfgIvrsExclusionRangeList , CFG_IOMMU_EXCLUSION_RANGE_LIST),
2618 #endif
2619 NULL
2620 };
2621 #endif
2622 #endif
2623#endif