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review.coreboot.org / coreboot / a03609b49600f05ec37e1796676954a3dc14faa3 / . / src / vendorcode / amd / agesa / f16kb / Include / PlatformInstall.h
blob: e989537df66876136c53496477060843c315b76f [file] [log] [blame]
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
15 */
16/*****************************************************************************
17 *
18 * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ***************************************************************************/
44
45/*****************************************************************************
46 *
47 * Start processing the user options: First, set default settings
48 *
49 ****************************************************************************/
50
51/* Available options for image builds.
52 *
53 * As part of the image build for each image, define the options below to select the
54 * AGESA entry points included in that image. Turn these on in your option c file, not
55 * here.
56 */
57// #define AGESA_ENTRY_INIT_RESET TRUE
58// #define AGESA_ENTRY_INIT_RECOVERY TRUE
59// #define AGESA_ENTRY_INIT_EARLY TRUE
60// #define AGESA_ENTRY_INIT_POST TRUE
61// #define AGESA_ENTRY_INIT_ENV TRUE
62// #define AGESA_ENTRY_INIT_MID TRUE
63// #define AGESA_ENTRY_INIT_LATE TRUE
64// #define AGESA_ENTRY_INIT_S3SAVE TRUE
65// #define AGESA_ENTRY_INIT_RESUME TRUE
66// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
67// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
68
69/* Defaults for private/internal build control settings */
70/* Available options for image builds.
71 *
72 * As part of the image build for each image, define the options below to select the
73 * AGESA entry points included in that image.
74 */
75
76VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
77 //ModuleHeaderSignature
78 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
79 Int32FromChar ('0', '0', '0', '0'),
80 //ModuleIdentifier[8]
81 AGESA_ID,
82 //ModuleVersion[12]
83 AGESA_VERSION_STRING,
84 //ModuleDispatcher
85 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
86 //NextBlock
87 NULL
88};
89
90/* Process user desired AGESA entry points */
91#ifndef AGESA_ENTRY_INIT_RESET
92 #define AGESA_ENTRY_INIT_RESET FALSE
93#endif
94
95#ifndef AGESA_ENTRY_INIT_RECOVERY
96 #define AGESA_ENTRY_INIT_RECOVERY FALSE
97#endif
98
99#ifndef AGESA_ENTRY_INIT_EARLY
100 #define AGESA_ENTRY_INIT_EARLY FALSE
101#endif
102
103#ifndef AGESA_ENTRY_INIT_POST
104 #define AGESA_ENTRY_INIT_POST FALSE
105#endif
106
107#ifndef AGESA_ENTRY_INIT_ENV
108 #define AGESA_ENTRY_INIT_ENV FALSE
109#endif
110
111#ifndef AGESA_ENTRY_INIT_MID
112 #define AGESA_ENTRY_INIT_MID FALSE
113#endif
114
115#ifndef AGESA_ENTRY_INIT_LATE
116 #define AGESA_ENTRY_INIT_LATE FALSE
117#endif
118
119#ifndef AGESA_ENTRY_INIT_S3SAVE
120 #define AGESA_ENTRY_INIT_S3SAVE FALSE
121#endif
122
123#ifndef AGESA_ENTRY_INIT_RESUME
124 #define AGESA_ENTRY_INIT_RESUME FALSE
125#endif
126
127#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
128 #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
129#endif
130
131#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
132 #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
133#endif
134
135/* Default the late AP entry point to off. It can be enabled
136 by any family that may need the late AP functionality, or
137 by any feature code that may need it. The IBVs no longer
138 have control over this entry point. */
139#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
140 #undef AGESA_ENTRY_LATE_RUN_AP_TASK
141#endif
142#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
143
144
145
146/* Process solution defined socket / family installations
147 *
148 * As part of the release package for each image, define the options below to select the
149 * AGESA processor support included in that image.
150 */
151
152/* Default sockets to off */
153#define OPTION_FT3_SOCKET_SUPPORT FALSE
154
155/* Default families to off */
156#define OPTION_FAMILY15H_MODEL_1x FALSE
157#define OPTION_FAMILY16H_MODEL_0x FALSE
158
159
160/* Enable the appropriate socket support */
161
162#ifdef INSTALL_FT3_SOCKET_SUPPORT
163 #if INSTALL_FT3_SOCKET_SUPPORT == TRUE
164 #undef OPTION_FT3_SOCKET_SUPPORT
165 #define OPTION_FT3_SOCKET_SUPPORT TRUE
166 #endif
167#endif
168
169
170
171// F16_0x is supported in FT3
172#ifdef INSTALL_FAMILY_16_MODEL_0x_SUPPORT
173 #if INSTALL_FAMILY_16_MODEL_0x_SUPPORT == TRUE
174 #undef OPTION_FAMILY16H
175 #define OPTION_FAMILY16H TRUE
176 #undef OPTION_FAMILY16H_MODEL_0x
177 #define OPTION_FAMILY16H_MODEL_0x TRUE
178 #endif
179#endif
180
181/* Turn off families not required by socket designations */
182#if (OPTION_FAMILY15H_MODEL_1x == FALSE)
183 #undef OPTION_FAMILY15H
184 #define OPTION_FAMILY15H FALSE
185#endif
186
187#if (OPTION_FAMILY16H_MODEL_0x == TRUE)
188 #if (OPTION_FT3_SOCKET_SUPPORT == FALSE)
189 #undef OPTION_FAMILY16H_MODEL_0x
190 #define OPTION_FAMILY16H_MODEL_0x FALSE
191 #endif
192#endif
193
194
195#if (OPTION_FAMILY16H_MODEL_0x == FALSE)
196 #undef OPTION_FAMILY16H
197 #define OPTION_FAMILY16H FALSE
198#endif
199
200
201#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
202 #if (OPTION_FAMILY16H_MODEL_0x == FALSE) && (OPTION_FAMILY16H_MODEL_3x == FALSE)
203 #error No FT3 supported families included in the build
204 #endif
205#endif
206
207
208/* Process AGESA private data
209 *
210 * Turn on appropriate CPU models and memory controllers,
211 * as well as some other memory controls.
212 */
213
214/* Default all models to off */
215#define OPTION_FAMILY15H_TN FALSE
216#define OPTION_FAMILY16H_KB FALSE
217#define OPTION_FAMILY15H_UNKNOWN FALSE
218
219/* Default all memory controllers to off */
220#define OPTION_MEMCTLR_TN FALSE
221#define OPTION_MEMCTLR_KB FALSE
222
223/* Default all memory controls to off */
224#define OPTION_HW_WRITE_LEV_TRAINING FALSE
225#define OPTION_SW_WRITE_LEV_TRAINING FALSE
226#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
227#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
228#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
229#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
230#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
231#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
232#define OPTION_MAX_RD_LAT_TRAINING FALSE
233#define OPTION_HW_DRAM_INIT FALSE
234#define OPTION_SW_DRAM_INIT FALSE
235#define OPTION_S3_MEM_SUPPORT FALSE
236#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
237#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
238#define OPTION_RDDQS_2D_TRAINING FALSE
239#define OPTION_PRE_MEM_INIT FALSE
240#define OPTION_POST_MEM_INIT FALSE
241
242/* Defaults for public user options */
243#define OPTION_UDIMMS FALSE
244#define OPTION_RDIMMS FALSE
245#define OPTION_SODIMMS FALSE
246#define OPTION_LRDIMMS FALSE
247#define OPTION_DDR2 FALSE
248#define OPTION_DDR3 FALSE
249#define OPTION_ECC FALSE
250#define OPTION_BANK_INTERLEAVE FALSE
251#define OPTION_DCT_INTERLEAVE FALSE
252#define OPTION_NODE_INTERLEAVE FALSE
253#define OPTION_PARALLEL_TRAINING FALSE
254#define OPTION_ONLINE_SPARE FALSE
255#define OPTION_MEM_RESTORE FALSE
256#define OPTION_DIMM_EXCLUDE FALSE
257#define OPTION_AMP FALSE
258#define OPTION_DATA_EYE FALSE
259#define OPTION_AGGRESSOR FALSE
260
261/* Default all CPU controls to off */
262#define OPTION_MULTISOCKET FALSE
263#define OPTION_CRAT FALSE
264#define OPTION_CDIT FALSE
265#define OPTION_SRAT FALSE
266#define OPTION_SLIT FALSE
267#define OPTION_HT_ASSIST FALSE
268#define OPTION_ATM_MODE FALSE
269#define OPTION_NBR_CACHE FALSE
270#define OPTION_CPU_CORELEVELING FALSE
271#define OPTION_MSG_BASED_C1E FALSE
272#define OPTION_CPU_CFOH FALSE
273#define OPTION_C6_STATE FALSE
274#define OPTION_IO_CSTATE FALSE
275#define OPTION_CPB FALSE
276#define OPTION_CPU_APM FALSE
277#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
278#define OPTION_CPU_PSTATE_HPC_MODE FALSE
279#define OPTION_CPU_TDP_LIMITING FALSE
280#define OPTION_CPU_PSI FALSE
281#define OPTION_CPU_HTC FALSE
282#define OPTION_S3SCRIPT FALSE
283#define OPTION_GFX_RECOVERY FALSE
284#define OPTION_CPU_SCS FALSE
285#define OPTION_PREFETCH_MODE FALSE
286
287/* Default FCH controls to off */
288#define FCH_SUPPORT FALSE
289
290/* Enable all private controls based on socket/family enables */
291
292#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
293 #if (OPTION_FAMILY16H_MODEL_0x == TRUE)
294 #undef FCH_SUPPORT
295 #define FCH_SUPPORT TRUE
296 #undef OPTION_FAMILY16H_KB
297 #define OPTION_FAMILY16H_KB TRUE
298 #undef OPTION_MEMCTLR_KB
299 #define OPTION_MEMCTLR_KB TRUE
300 #undef OPTION_HW_WRITE_LEV_TRAINING
301 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
302 #undef OPTION_CONTINOUS_PATTERN_GENERATION
303 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
304 #undef OPTION_HW_DQS_REC_EN_TRAINING
305 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
306 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
307 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
308 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
309 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
310 #undef OPTION_RDDQS_2D_TRAINING
311 #define OPTION_RDDQS_2D_TRAINING TRUE
312 #undef OPTION_MAX_RD_LAT_TRAINING
313 #define OPTION_MAX_RD_LAT_TRAINING TRUE
314 #undef OPTION_SW_DRAM_INIT
315 #define OPTION_SW_DRAM_INIT TRUE
316 #undef OPTION_S3_MEM_SUPPORT
317 #define OPTION_S3_MEM_SUPPORT TRUE
318 #undef OPTION_GFX_RECOVERY
319 #define OPTION_GFX_RECOVERY TRUE
320 #undef OPTION_CPU_CORELEVELING
321 #define OPTION_CPU_CORELEVELING TRUE
322 #undef OPTION_C6_STATE
323 #define OPTION_C6_STATE TRUE
324 #undef OPTION_IO_CSTATE
325 #define OPTION_IO_CSTATE TRUE
326 #undef OPTION_CPU_CFOH
327 #define OPTION_CPU_CFOH TRUE
328 #undef OPTION_CPU_APM
329 #define OPTION_CPU_APM TRUE
330 #undef OPTION_CPB
331 #define OPTION_CPB TRUE
332 #undef OPTION_CPU_HTC
333 #define OPTION_CPU_HTC TRUE
334 #undef OPTION_CPU_PSI
335 #define OPTION_CPU_PSI TRUE
336 #undef OPTION_CDIT
337 #define OPTION_CDIT TRUE
338 #undef OPTION_CRAT
339 #define OPTION_CRAT TRUE
340 #undef OPTION_CPU_SCS
341 #define OPTION_CPU_SCS TRUE
342 #undef OPTION_S3SCRIPT
343 #define OPTION_S3SCRIPT TRUE
344 ///@todo
345 //#undef OPTION_PREFETCH_MODE
346 //#define OPTION_PREFETCH_MODE TRUE
347 #undef OPTION_UDIMMS
348 #define OPTION_UDIMMS TRUE
349 #undef OPTION_SODIMMS
350 #define OPTION_SODIMMS TRUE
351 #undef OPTION_DDR3
352 #define OPTION_DDR3 TRUE
353 #undef OPTION_ECC
354 #define OPTION_ECC TRUE
355 #undef OPTION_BANK_INTERLEAVE
356 #define OPTION_BANK_INTERLEAVE TRUE
357 #undef OPTION_DCT_INTERLEAVE
358 #define OPTION_DCT_INTERLEAVE TRUE
359 #undef OPTION_MEM_RESTORE
360 #define OPTION_MEM_RESTORE TRUE
361 #undef OPTION_DIMM_EXCLUDE
362 #define OPTION_DIMM_EXCLUDE TRUE
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]363 #ifndef OPTION_MICROSERVER
364 #define OPTION_MICROSERVER FALSE
365 #endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]366 #endif
367#endif
368
369
370#if (OPTION_FAMILY16H_KB == TRUE)
371 #undef GNB_SUPPORT
372 #define GNB_SUPPORT TRUE
373#endif
374
375#define OPTION_ACPI_PSTATES TRUE
376#define OPTION_WHEA TRUE
377#define OPTION_DMI TRUE
378#define OPTION_EARLY_SAMPLES FALSE
379#define CFG_ACPI_PSTATES_PPC TRUE
380#define CFG_ACPI_PSTATES_PCT TRUE
381#define CFG_ACPI_PSTATES_PSD TRUE
382#define CFG_ACPI_PSTATES_PSS TRUE
383#define CFG_ACPI_PSTATES_XPSS TRUE
384#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
385#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
386#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
387#define OPTION_ALIB TRUE
388/*---------------------------------------------------------------------------
389 * Processing the options: Second, process the user's selections
390 *--------------------------------------------------------------------------*/
391#ifdef BLDOPT_REMOVE_DDR3_SUPPORT
392 #if BLDOPT_REMOVE_DDR3_SUPPORT == TRUE
393 #undef OPTION_DDR3
394 #define OPTION_DDR3 FALSE
395 #endif
396#endif
397#if ((OPTION_DDR3 == FALSE))
398 #error BLDOPT: No DIMM type support selected. BLDOPT_REMOVE_DDR3_SUPPORT must be FALSE.
399#endif
400#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
401 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
402 #undef OPTION_MULTISOCKET
403 #define OPTION_MULTISOCKET FALSE
404 #endif
405#endif
406#ifdef BLDOPT_REMOVE_ECC_SUPPORT
407 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
408 #undef OPTION_ECC
409 #define OPTION_ECC FALSE
410 #endif
411#endif
412#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
413 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
414 #undef OPTION_UDIMMS
415 #define OPTION_UDIMMS FALSE
416 #endif
417#endif
418#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
419 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
420 #undef OPTION_RDIMMS
421 #define OPTION_RDIMMS FALSE
422 #endif
423#endif
424#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
425 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
426 #undef OPTION_SODIMMS
427 #define OPTION_SODIMMS FALSE
428 #endif
429#endif
430#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
431 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
432 #undef OPTION_LRDIMMS
433 #define OPTION_LRDIMMS FALSE
434 #endif
435#endif
436#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
437 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
438 #undef OPTION_BANK_INTERLEAVE
439 #define OPTION_BANK_INTERLEAVE FALSE
440 #endif
441#endif
442#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
443 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
444 #undef OPTION_DCT_INTERLEAVE
445 #define OPTION_DCT_INTERLEAVE FALSE
446 #endif
447#endif
448#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
449 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
450 #undef OPTION_NODE_INTERLEAVE
451 #define OPTION_NODE_INTERLEAVE FALSE
452 #endif
453#endif
454#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
455 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
456 #undef OPTION_PARALLEL_TRAINING
457 #define OPTION_PARALLEL_TRAINING FALSE
458 #endif
459#endif
460#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
461 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
462 #undef OPTION_ONLINE_SPARE
463 #define OPTION_ONLINE_SPARE FALSE
464 #endif
465#endif
466#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
467 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
468 #undef OPTION_MEM_RESTORE
469 #define OPTION_MEM_RESTORE FALSE
470 #endif
471#endif
472#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
473 #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
474 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
475 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
476 #endif
477#endif
478#ifdef BLDOPT_REMOVE_ACPI_PSTATES
479 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
480 #undef OPTION_ACPI_PSTATES
481 #define OPTION_ACPI_PSTATES FALSE
482 #endif
483#endif
484#ifdef BLDOPT_REMOVE_CRAT
485 #if BLDOPT_REMOVE_CRAT == TRUE
486 #undef OPTION_CRAT
487 #define OPTION_CRAT FALSE
488 #endif
489#endif
490#ifdef BLDOPT_REMOVE_CDIT
491 #if BLDOPT_REMOVE_CDIT == TRUE
492 #undef OPTION_CDIT
493 #define OPTION_CDIT FALSE
494 #endif
495#endif
496#ifdef BLDOPT_REMOVE_SRAT
497 #if BLDOPT_REMOVE_SRAT == TRUE
498 #undef OPTION_SRAT
499 #define OPTION_SRAT FALSE
500 #endif
501#endif
502#ifdef BLDOPT_REMOVE_SLIT
503 #if BLDOPT_REMOVE_SLIT == TRUE
504 #undef OPTION_SLIT
505 #define OPTION_SLIT FALSE
506 #endif
507#endif
508#ifdef BLDOPT_REMOVE_WHEA
509 #if BLDOPT_REMOVE_WHEA == TRUE
510 #undef OPTION_WHEA
511 #define OPTION_WHEA FALSE
512 #endif
513#endif
514#ifdef BLDOPT_REMOVE_DMI
515 #if BLDOPT_REMOVE_DMI == TRUE
516 #undef OPTION_DMI
517 #define OPTION_DMI FALSE
518 #endif
519#endif
520#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
521 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
522 #undef OPTION_ADDR_TO_CS_TRANSLATOR
523 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
524 #endif
525#endif
526#ifdef BLDOPT_REMOVE_AMP_SUPPORT
527 #if BLDOPT_REMOVE_AMP_SUPPORT == TRUE
528 #undef OPTION_AMP
529 #define OPTION_AMP FALSE
530 #endif
531#endif
532
533#ifdef OPTION_RDDQS_2D_TRAINING
534 #if OPTION_RDDQS_2D_TRAINING == FALSE
535 #undef OPTION_DATA_EYE
536 #define OPTION_DATA_EYE FALSE
537 #else
538 #ifdef BLDOPT_REMOVE_DATA_EYE
539 #if BLDOPT_REMOVE_DATA_EYE == TRUE
540 #undef OPTION_DATA_EYE
541 #define OPTION_DATA_EYE FALSE
542 #endif
543 #endif
544 #endif
545#else
546 #undef OPTION_DATA_EYE
547 #define OPTION_DATA_EYE FALSE
548#endif
549
550#ifdef BLDOPT_REMOVE_HT_ASSIST
551 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
552 #undef OPTION_HT_ASSIST
553 #define OPTION_HT_ASSIST FALSE
554 #endif
555#endif
556
557#ifdef BLDOPT_REMOVE_ATM_MODE
558 #if BLDOPT_REMOVE_ATM_MODE == TRUE
559 #undef OPTION_ATM_MODE
560 #define OPTION_ATM_MODE FALSE
561 #endif
562#endif
563
564#ifdef BLDOPT_REMOVE_NEIGHBOR_CACHE
565 #if BLDOPT_REMOVE_NEIGHBOR_CACHE == TRUE
566 #undef OPTION_NBR_CACHE
567 #define OPTION_NBR_CACHE FALSE
568 #endif
569#endif
570
571#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
572 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
573 #undef OPTION_MSG_BASED_C1E
574 #define OPTION_MSG_BASED_C1E FALSE
575 #endif
576#endif
577
578#ifdef BLDOPT_REMOVE_C6_STATE
579 #if BLDOPT_REMOVE_C6_STATE == TRUE
580 #undef OPTION_C6_STATE
581 #define OPTION_C6_STATE FALSE
582 #endif
583#endif
584
585#ifdef BLDOPT_REMOVE_GFX_RECOVERY
586 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
587 #undef OPTION_GFX_RECOVERY
588 #define OPTION_GFX_RECOVERY FALSE
589 #endif
590#endif
591
592#ifdef BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING
593 #if BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING == TRUE
594 #undef OPTION_RDDQS_2D_TRAINING
595 #define OPTION_RDDQS_2D_TRAINING FALSE
596 #endif
597#endif
598
599#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
600 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
601 #undef CFG_ACPI_PSTATES_PPC
602 #define CFG_ACPI_PSTATES_PPC FALSE
603 #endif
604#endif
605
606#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
607 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
608 #undef CFG_ACPI_PSTATES_PCT
609 #define CFG_ACPI_PSTATES_PCT FALSE
610 #endif
611#endif
612
613#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
614 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
615 #undef CFG_ACPI_PSTATES_PSD
616 #define CFG_ACPI_PSTATES_PSD FALSE
617 #endif
618#endif
619
620#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
621 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
622 #undef CFG_ACPI_PSTATES_PSS
623 #define CFG_ACPI_PSTATES_PSS FALSE
624 #endif
625#endif
626
627#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
628 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
629 #undef CFG_ACPI_PSTATES_XPSS
630 #define CFG_ACPI_PSTATES_XPSS FALSE
631 #endif
632#endif
633
634#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
635 #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE
636 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
637 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
638 #endif
639#endif
640
641#ifdef BLDOPT_REMOVE_AGGRESSOR
642 #if BLDOPT_REMOVE_AGGRESSOR == TRUE
643 #undef OPTION_AGGRESSOR
644 #define OPTION_AGGRESSOR FALSE
645 #endif
646#endif
647
648#ifdef BLDCFG_PSTATE_HPC_MODE
649 #if BLDCFG_PSTATE_HPC_MODE == TRUE
650 #undef OPTION_CPU_PSTATE_HPC_MODE
651 #define OPTION_CPU_PSTATE_HPC_MODE TRUE
652 #endif
653#endif
654
655#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
656 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
657 #undef CFG_ACPI_PSTATE_PSD_INDPX
658 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
659 #endif
660#endif
661
662#ifdef BLDCFG_ACPI_PSTATES_PSD_POLICY
663 #define CFG_ACPI_PSTATES_PSD_POLICY (BLDCFG_ACPI_PSTATES_PSD_POLICY)
664#else
665 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyProcessorDefault
666#endif
667
668#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
669 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
670 #undef CFG_VRM_HIGH_SPEED_ENABLE
671 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
672 #endif
673#endif
674
675#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
676 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
677 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
678 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
679 #endif
680#endif
681
682#ifdef BLDCFG_STARTING_BUSNUM
683 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
684#else
685 #define CFG_STARTING_BUSNUM (0)
686#endif
687
688#ifdef BLDCFG_AMD_PLATFORM_TYPE
689 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
690#else
691 #define CFG_AMD_PLATFORM_TYPE 0
692#endif
693
694CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
695
696#ifdef BLDCFG_MAXIMUM_BUSNUM
697 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
698#else
699 #define CFG_MAXIMUM_BUSNUM (0xF8)
700#endif
701
702#ifdef BLDCFG_ALLOCATED_BUSNUM
703 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
704#else
705 #define CFG_ALLOCATED_BUSNUM (0x20)
706#endif
707
708#ifdef BLDCFG_BUID_SWAP_LIST
709 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
710#else
711 #define CFG_BUID_SWAP_LIST (NULL)
712#endif
713
714#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
715 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
716#else
717 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
718#endif
719
720#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
721 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
722#else
723 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
724#endif
725
726#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
727 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
728#else
729 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
730#endif
731
732#ifdef BLDCFG_BUS_NUMBERS_LIST
733 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
734#else
735 #define CFG_BUS_NUMBERS_LIST (NULL)
736#endif
737
738#ifdef BLDCFG_IGNORE_LINK_LIST
739 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
740#else
741 #define CFG_IGNORE_LINK_LIST (NULL)
742#endif
743
744#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
745 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
746#else
747 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
748#endif
749
750#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
751 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
752#else
753 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
754#endif
755
756#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
757 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
758#else
759 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
760#endif
761
762#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
763 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
764#else
765 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
766#endif
767
768#ifdef BLDCFG_USE_HT_ASSIST
769 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
770#else
771 #define CFG_USE_HT_ASSIST (TRUE)
772#endif
773
774#ifdef BLDCFG_USE_ATM_MODE
775 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
776#else
777 #define CFG_USE_ATM_MODE (TRUE)
778#endif
779
780#ifdef BLDCFG_USE_NEIGHBOR_CACHE
781 #define CFG_USE_NBR_CACHE (BLDCFG_USE_NEIGHBOR_CACHE)
782#else
783 #define CFG_USE_NBR_CACHE (TRUE)
784#endif
785
786#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
787 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
788#else
789 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
790#endif
791
792#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
793 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
794#else
795 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO)
796#endif
797
798#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
799 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
800#else
801 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO)
802#endif
803
804#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
805 #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
806#else
807 #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO)
808#endif
809
810#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
811 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
812#else
813 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
814#endif
815
816#ifdef BLDCFG_VRM_CURRENT_LIMIT
817 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
818#else
819 #define CFG_VRM_CURRENT_LIMIT 0
820#endif
821
822#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
823 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
824#else
825 #define CFG_VRM_LOW_POWER_THRESHOLD 0
826#endif
827
828#ifdef BLDCFG_VRM_SLEW_RATE
829 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
830#else
831 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
832#endif
833
834#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
835 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
836#else
837 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0)
838#endif
839
840#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
841 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
842#else
843 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0)
844#endif
845
846#ifdef BLDCFG_VRM_SVI_OCP_LEVEL
847 #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL
848#else
849 #define CFG_VRM_SVI_OCP_LEVEL 0
850#endif
851
852#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
853 #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL
854#else
855 #define CFG_VRM_NB_SVI_OCP_LEVEL 0
856#endif
857
858#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
859 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
860#else
861 #define CFG_VRM_NB_CURRENT_LIMIT (0)
862#endif
863
864#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
865 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
866#else
867 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
868#endif
869
870#ifdef BLDCFG_VRM_NB_SLEW_RATE
871 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
872#else
873 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
874#endif
875
876#ifdef BLDCFG_PLAT_NUM_IO_APICS
877 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
878#else
879 #define CFG_PLAT_NUM_IO_APICS 0
880#endif
881
882#ifdef BLDCFG_MEM_INIT_PSTATE
883 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
884#else
885 #define CFG_MEM_INIT_PSTATE 0
886#endif
887
888#ifdef BLDCFG_PLATFORM_C1E_MODE
889 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
890#else
891 #define CFG_C1E_MODE C1eModeDisabled
892#endif
893
894#ifdef BLDCFG_PLATFORM_C1E_OPDATA
895 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
896#else
897 #define CFG_C1E_OPDATA 0
898#endif
899
900#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
901 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
902#else
903 #define CFG_C1E_OPDATA1 0
904#endif
905
906#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
907 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
908#else
909 #define CFG_C1E_OPDATA2 0
910#endif
911
912#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
913 #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3
914#else
915 #define CFG_C1E_OPDATA3 0
916#endif
917
918#ifdef BLDCFG_PLATFORM_CSTATE_MODE
919 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
920#else
921 #define CFG_CSTATE_MODE CStateModeC6
922#endif
923
924#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
925 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
926#else
927 #define CFG_CSTATE_OPDATA 0
928#endif
929
930#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
931 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
932#else
933 #define CFG_CSTATE_IO_BASE_ADDRESS 0
934#endif
935
936#ifdef BLDCFG_PLATFORM_CPB_MODE
937 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
938#else
939 #define CFG_CPB_MODE CpbModeAuto
940#endif
941
942#ifdef BLDCFG_CORE_LEVELING_MODE
943 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
944#else
945 #define CFG_CORE_LEVELING_MODE 0
946#endif
947
948#ifdef BLDCFG_AMD_TDP_LIMIT
949 #define CFG_AMD_POWER_CEILING BLDCFG_AMD_TDP_LIMIT
950#else
951 #define CFG_AMD_POWER_CEILING 0
952#endif
953
954#ifdef BLDCFG_HEAP_DRAM_ADDRESS
955 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
956#else
957 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
958#endif
959
960#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
961 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
962#else
963 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
964#endif
965
966#ifdef BLDCFG_MEMORY_MODE_UNGANGED
967 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
968#else
969 #define CFG_MEMORY_MODE_UNGANGED TRUE
970#endif
971
972#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
973 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
974#else
975 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
976#endif
977
978#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
979 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
980#else
981 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
982#endif
983
984#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
985 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
986#else
987 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
988#endif
989
990#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
991 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
992#else
993 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
994#endif
995
996#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
997 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
998#else
999 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
1000#endif
1001
1002#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
1003 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
1004#else
1005 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
1006#endif
1007
1008#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1009 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1010#else
1011 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
1012#endif
1013
1014#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1015 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1016#else
1017 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
1018#endif
1019
1020#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1021 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1022#else
1023 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
1024#endif
1025
1026#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1027 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1028#else
1029 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
1030#endif
1031
1032#ifdef BLDCFG_MEMORY_POWER_DOWN
1033 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
1034#else
1035 #define CFG_MEMORY_POWER_DOWN FALSE
1036#endif
1037
1038#ifdef BLDCFG_POWER_DOWN_MODE
1039 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
1040#else
1041 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
1042#endif
1043
1044#ifdef BLDCFG_ONLINE_SPARE
1045 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
1046#else
1047 #define CFG_ONLINE_SPARE FALSE
1048#endif
1049
1050#ifdef BLDCFG_MEMORY_PARITY_ENABLE
1051 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
1052#else
1053 #define CFG_MEMORY_PARITY_ENABLE FALSE
1054#endif
1055
1056#ifdef BLDCFG_BANK_SWIZZLE
1057 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
1058#else
1059 #define CFG_BANK_SWIZZLE TRUE
1060#endif
1061
1062#ifdef BLDCFG_TIMING_MODE_SELECT
1063 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1064#else
1065 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1066#endif
1067
1068#ifdef BLDCFG_MEMORY_CLOCK_SELECT
1069 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1070#else
1071 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
1072#endif
1073
1074#ifdef BLDCFG_DQS_TRAINING_CONTROL
1075 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1076#else
1077 #define CFG_DQS_TRAINING_CONTROL TRUE
1078#endif
1079
1080#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1081 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1082#else
1083 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1084#endif
1085
1086#ifdef BLDCFG_USE_BURST_MODE
1087 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1088#else
1089 #define CFG_USE_BURST_MODE FALSE
1090#endif
1091
1092#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1093 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1094#else
1095 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1096#endif
1097
1098#ifdef BLDCFG_ENABLE_ECC_FEATURE
1099 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1100#else
1101 #define CFG_ENABLE_ECC_FEATURE TRUE
1102#endif
1103
1104#ifdef BLDCFG_ECC_REDIRECTION
1105 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1106#else
1107 #define CFG_ECC_REDIRECTION FALSE
1108#endif
1109
1110#ifdef BLDCFG_SCRUB_DRAM_RATE
1111 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1112#else
1113 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
1114#endif
1115
1116#ifdef BLDCFG_SCRUB_L2_RATE
1117 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1118#else
1119 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
1120#endif
1121
1122#ifdef BLDCFG_SCRUB_L3_RATE
1123 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1124#else
1125 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
1126#endif
1127
1128#ifdef BLDCFG_SCRUB_IC_RATE
1129 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1130#else
1131 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
1132#endif
1133
1134#ifdef BLDCFG_SCRUB_DC_RATE
1135 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1136#else
1137 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
1138#endif
1139
1140#ifdef BLDCFG_ECC_SYNC_FLOOD
1141 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1142#else
1143 #define CFG_ECC_SYNC_FLOOD TRUE
1144#endif
1145
1146#ifdef BLDCFG_ECC_SYMBOL_SIZE
1147 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1148#else
1149 #define CFG_ECC_SYMBOL_SIZE 0
1150#endif
1151
1152#ifdef BLDCFG_1GB_ALIGN
1153 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1154#else
1155 #define CFG_1GB_ALIGN FALSE
1156#endif
1157
1158#ifdef BLDCFG_UMA_ALLOCATION_MODE
1159 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1160#else
1161 #define CFG_UMA_MODE UMA_AUTO
1162#endif
1163
1164#ifdef BLDCFG_FORCE_TRAINING_MODE
1165 #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE
1166#else
1167 #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO
1168#endif
1169
1170#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1171 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1172#else
1173 #define CFG_UMA_SIZE 0
1174#endif
1175
1176#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1177 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1178#else
1179 #define CFG_UMA_ABOVE4G FALSE
1180#endif
1181
1182#ifdef BLDCFG_UMA_ALIGNMENT
1183 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1184#else
1185 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1186#endif
1187
1188#ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1189 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1190#else
1191 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG DDR3_TECHNOLOGY
1192#endif
1193
1194#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1195 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1196#else
1197 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1198#endif
1199
1200#ifdef BLDCFG_S3_LATE_RESTORE
1201 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1202#else
1203 #define CFG_S3_LATE_RESTORE TRUE
1204#endif
1205
1206#ifdef BLDCFG_USE_32_BYTE_REFRESH
1207 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1208#else
1209 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1210#endif
1211
1212#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1213 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1214#else
1215 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1216#endif
1217
1218#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1219 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1220#else
1221 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1222#endif
1223
1224#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1225 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1226#else
1227 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1228#endif
1229
1230#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1231 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1232#else
1233 #define CFG_GNB_HD_AUDIO TRUE
1234#endif
1235
1236#ifdef BLDCFG_CFG_ABM_SUPPORT
1237 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1238#else
1239 #define CFG_ABM_SUPPORT FALSE
1240#endif
1241
1242#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1243 #define CFG_DYNAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1244#else
1245 #define CFG_DYNAMIC_REFRESH_RATE 0
1246#endif
1247
1248#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1249 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1250#else
1251 #define CFG_LCD_BACK_LIGHT_CONTROL 200
1252#endif
1253
1254#ifdef BLDCFG_STEREO_3D_PINOUT
1255 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1256#else
1257 #define CFG_GNB_STEREO_3D_PINOUT 0
1258#endif
1259
1260#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
1261 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT
1262#else
1263 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE
1264#endif
1265
1266// Define pin configuration for SYNCFLOOD
1267// Default to FALSE (Use pin as SYNCFLOOD)
1268#ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI
1269 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI BLDCFG_USE_SYNCFLOOD_AS_NMI
1270#else
1271 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI FALSE
1272#endif
1273
1274#ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1275 #define CFG_GNB_THERMAL_SENSOR_CORRECTION BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1276#else
1277 #define CFG_GNB_THERMAL_SENSOR_CORRECTION 0
1278#endif
1279
1280#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1281 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1282#else
1283 #define CFG_GNB_IGPU_SSID 0
1284#endif
1285
1286#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1287 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1288#else
1289 #define CFG_GNB_HDAUDIO_SSID 0
1290#endif
1291
1292#ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1293 #define CFG_IGPU_ENABLE_DISABLE_POLICY BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1294#else
1295 #define CFG_IGPU_ENABLE_DISABLE_POLICY IGPU_DISABLE_AUTO
1296#endif
1297
1298#ifdef BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1299 #define CFG_GNB_PCIE_SSID BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1300#else
1301 #define CFG_GNB_PCIE_SSID 0x12341022ul
1302#endif
1303
1304#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1305 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1306#else
1307 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1308#endif
1309
1310#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1311 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1312#else
1313 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1314#endif
1315
1316#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1317 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1318#else
1319 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1320#endif
1321
1322#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1323 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1324#else
1325 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000ul
1326#endif
1327
1328#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1329 #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1330#else
1331 #define CFG_ENABLE_EXTERNAL_VREF FALSE
1332#endif
1333
1334#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1335 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1336 #undef OPTION_EARLY_SAMPLES
1337 #define OPTION_EARLY_SAMPLES FALSE
1338 #else
1339 #undef OPTION_EARLY_SAMPLES
1340 #define OPTION_EARLY_SAMPLES TRUE
1341 #endif
1342#endif
1343
1344#ifdef BLDOPT_REMOVE_ALIB
1345 #if BLDOPT_REMOVE_ALIB == TRUE
1346 #undef OPTION_ALIB
1347 #define OPTION_ALIB FALSE
1348 #else
1349 #undef OPTION_ALIB
1350 #define OPTION_ALIB TRUE
1351 #endif
1352#endif
1353
1354#ifdef BLDOPT_REMOVE_FCH_COMPONENT
1355 #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
1356 #undef FCH_SUPPORT
1357 #define FCH_SUPPORT FALSE
1358 #endif
1359#endif
1360
1361#ifdef BLDCFG_IOMMU_SUPPORT
1362 #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT
1363#else
1364 #define CFG_IOMMU_SUPPORT TRUE
1365#endif
1366
1367#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1368 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1369#else
1370 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0
1371#endif
1372
1373#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1374 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1375#else
1376 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0
1377#endif
1378
1379#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1380 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1381#else
1382 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0
1383#endif
1384
1385#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1386 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1387#else
1388 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0
1389#endif
1390
1391#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1392 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1393#else
1394 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0
1395#endif
1396
1397#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1398 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1399#else
1400 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
1401#endif
1402
1403#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1404 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1405#else
1406 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
1407#endif
1408
1409#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1410 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1411#else
1412 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0
1413#endif
1414
1415#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1416 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1417#else
1418 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0
1419#endif
1420
1421
1422// BLDCFG_LVDS_24BBP_PANEL_MODE
1423// This specifies the LVDS 24 BBP mode.
1424// 0 - Use LDI mode (default).
1425// 1 - Use FPDI mode.
1426#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
1427 #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE
1428#else
1429 #define CFG_LVDS_24BBP_PANEL_MODE 0
1430#endif
1431
1432#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1433 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1434#else
1435 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1436#endif
1437
1438#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1439 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1440#else
1441 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1442#endif
1443
1444#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1445 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1446#else
1447 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1448#endif
1449
1450#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1451 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1452#else
1453 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1454#endif
1455
1456#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1457 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1458#else
1459 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1460#endif
1461
1462#ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1463 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1464#else
1465 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE FALSE
1466#endif
1467
1468#ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1469 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1470#else
1471 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT 0
1472#endif
1473
1474#ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1475 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1476#else
1477 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE FALSE
1478#endif
1479
1480#ifdef BLDCFG_DP_FIXED_VOLT_SWING
1481 #define CFG_DP_FIXED_VOLT_SWING BLDCFG_DP_FIXED_VOLT_SWING
1482#else
1483 #define CFG_DP_FIXED_VOLT_SWING 0
1484#endif
1485
1486#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1487 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1488#else
1489 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1490#endif
1491
1492#ifdef BLDCFG_NB_PSTATES_SUPPORTED
1493 #define CFG_NB_PSTATES_SUPPORTED (BLDCFG_NB_PSTATES_SUPPORTED)
1494#else
1495 #define CFG_NB_PSTATES_SUPPORTED (TRUE)
1496#endif
1497
1498#ifdef BLDCFG_HTC_TEMPERATURE_LIMIT
1499 #define CFG_HTC_TEMPERATURE_LIMIT (BLDCFG_HTC_TEMPERATURE_LIMIT)
1500#else
1501 #define CFG_HTC_TEMPERATURE_LIMIT (0)
1502#endif
1503
1504#ifdef BLDCFG_LHTC_TEMPERATURE_LIMIT
1505 #define CFG_LHTC_TEMPERATURE_LIMIT (BLDCFG_LHTC_TEMPERATURE_LIMIT)
1506#else
1507 #define CFG_LHTC_TEMPERATURE_LIMIT (0)
1508#endif
1509
1510#ifdef BLDCFG_PCI_MMIO_BASE
1511 #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
1512#else
1513 #define CFG_PCI_MMIO_BASE (0)
1514#endif
1515
1516#ifdef BLDCFG_PCI_MMIO_SIZE
1517 #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
1518#else
1519 #define CFG_PCI_MMIO_SIZE (0)
1520#endif
1521
1522#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1523 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1524#else
1525 #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
1526#endif
1527
1528#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
1529 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
1530#else
1531 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
1532#endif
1533
1534#ifdef BLDCFG_HYBRID_BOOST_ENABLE
1535 #define CFG_HYBRID_BOOST_ENABLE BLDCFG_HYBRID_BOOST_ENABLE
1536#else
1537 #define CFG_HYBRID_BOOST_ENABLE TRUE
1538#endif
1539
1540#ifdef BLDCFG_GNB_IOAPIC_ADDRESS
1541 #define CFG_GNB_IOAPIC_ADDRESS BLDCFG_GNB_IOAPIC_ADDRESS
1542#else
1543 #define CFG_GNB_IOAPIC_ADDRESS NULL
1544#endif
1545
1546#ifdef BLDCFG_GNB_IOMMU_ADDRESS
1547 #define CFG_GNB_IOMMU_ADDRESS BLDCFG_GNB_IOMMU_ADDRESS
1548#else
1549 #define CFG_GNB_IOMMU_ADDRESS NULL
1550#endif
1551
1552#ifdef BLDCFG_ENABLE_DATA_EYE
1553 #define CFG_ENABLE_DATA_EYE BLDCFG_ENABLE_DATA_EYE
1554#else
1555 #define CFG_ENABLE_DATA_EYE TRUE
1556#endif
1557
1558#ifdef BLDCFG_ACPI_SET_OEM_ID
1559 #define CFG_ACPI_SET_OEM_ID BLDCFG_ACPI_SET_OEM_ID
1560#else
1561 #define CFG_ACPI_SET_OEM_ID 'A','M','D',' ',' ',' '
1562#endif
1563
1564#ifdef BLDCFG_ACPI_SET_OEM_TABLE_ID
1565 #define CFG_ACPI_SET_OEM_TABLE_ID BLDCFG_ACPI_SET_OEM_TABLE_ID
1566#else
1567 #define CFG_ACPI_SET_OEM_TABLE_ID 'A','G','E','S','A',' ',' ',' '
1568#endif
1569
1570#ifdef BLDCFG_DOCKED_TDP_HEADROOM
1571 #define CFG_DOCKED_TDP_HEADROOM BLDCFG_DOCKED_TDP_HEADROOM
1572#else
1573 #define CFG_DOCKED_TDP_HEADROOM TRUE
1574#endif
1575
1576#ifdef BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1577 #define CFG_DRAM_DOUBLE_REFRESH_RATE BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1578#else
1579 #define CFG_DRAM_DOUBLE_REFRESH_RATE FALSE
1580#endif
1581
1582/*---------------------------------------------------------------------------
1583 * Processing the options: Third, perform the option cross checks
1584 *--------------------------------------------------------------------------*/
1585// Assure that at least one type of memory support is included
1586#if OPTION_UDIMMS == FALSE
1587 #if OPTION_RDIMMS == FALSE
1588 #if OPTION_SODIMMS == FALSE
1589 #if OPTION_LRDIMMS == FALSE
1590 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1591 #endif
1592 #endif
1593 #endif
1594#endif
1595// Ensure at least one dimm type is capable
1596#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1597 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1598 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1599 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1600 #error BLDCFG: No dimm type is capable
1601 #endif
1602 #endif
1603 #endif
1604#endif
1605// Check LRDIMM CODE and LRDIMM CFG item
1606#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1607 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1608 #error Warning: LRDIMM capability is false, but LRIDMM support code included
1609 #endif
1610#endif
1611// Turn off multi-socket based features if only one node...
1612#if OPTION_MULTISOCKET == FALSE
1613 #undef OPTION_PARALLEL_TRAINING
1614 #define OPTION_PARALLEL_TRAINING FALSE
1615 #undef OPTION_NODE_INTERLEAVE
1616 #define OPTION_NODE_INTERLEAVE FALSE
1617#endif
1618// Ensure the frequency limit is valid
1619#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY)
1620 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY)
1621 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY)
1622 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY)
1623 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY)
1624 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY)
1625 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY)
1626 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY)
1627 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY)
1628 #error BLDCFG: Unsupported memory bus frequency
1629 #endif
1630 #endif
1631 #endif
1632 #endif
1633 #endif
1634 #endif
1635 #endif
1636 #endif
1637#endif
1638// Ensure timing mode is valid
1639#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
1640 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
1641 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
1642 #error BLDCFG: Invalid timing mode is set
1643 #endif
1644 #endif
1645#endif
1646// Ensure the scrub rate is valid
1647#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
1648 #error BLDCFG: Unsupported dram scrub rate set
1649#endif
1650#if CFG_SCRUB_L2_RATE > 0x16
1651 #error BLDCFG: Unsupported L2 scrubber rate set
1652#endif
1653#if CFG_SCRUB_L3_RATE > 0x16
1654 #error BLDCFG: unsupported L3 scrubber rate set
1655#endif
1656#if CFG_SCRUB_IC_RATE > 0x16
1657 #error BLDCFG: Unsupported Instruction cache scrub rate set
1658#endif
1659#if CFG_SCRUB_DC_RATE > 0x16
1660 #error BLDCFG: Unsupported Dcache scrub rate set
1661#endif
1662// Ensure Quad rank dimm type is valid
1663#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
1664 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
1665 #error BLDCFG: Invalid quad rank dimm type set
1666 #endif
1667#endif
1668// Ensure ECC symbol size is valid
1669#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
1670 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
1671 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
1672 #error BLDCFG: Invalid Ecc symbol size set
1673 #endif
1674 #endif
1675#endif
1676// Ensure power down mode is valid
1677#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
1678 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
1679 #if AGESA_ENTRY_INIT_POST == TRUE
1680 #error BLDCFG: Invalid power down mode set
1681 #endif
1682 #endif
1683#endif
1684
1685// Ensure P-state dependence settings do not conflict
1686#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyDependent) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1687 #error BLDCFG: Conflict P-state dependency settings between BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT and BLDCFG_ACPI_PSTATES_PSD_POLICY.
1688#endif
1689
1690#if ((CFG_HTC_TEMPERATURE_LIMIT == 0) && (CFG_LHTC_TEMPERATURE_LIMIT != 0))
1691 #error BLDCFG: Cannot define BLDCFG_LHTC_TEMPERATURE_LIMIT unless BLDCFG_HTC_TEMPERATURE_LIMIT is also not zero.
1692#endif
1693
1694#if ((CFG_LHTC_TEMPERATURE_LIMIT == 0) && (CFG_HTC_TEMPERATURE_LIMIT != 0))
1695 #error BLDCFG: Cannot define BLDCFG_HTC_TEMPERATURE_LIMIT unless BLDCFG_LHTC_TEMPERATURE_LIMIT is also not zero.
1696#endif
1697
1698
1699
1700/*****************************************************************************
1701 *
1702 * Process the option logic, setting local control variables
1703 *
1704 ****************************************************************************/
1705#if OPTION_ACPI_PSTATES == TRUE
1706 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
1707 #define OPTFCN_GATHER_DATA PStateGatherData
1708 #if OPTION_MULTISOCKET == TRUE
1709 #define OPTFCN_PSTATE_LEVELING PStateLeveling
1710 #else
1711 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1712 #endif
1713#else
1714 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
1715 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
1716 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1717#endif
1718
1719// Consolidate P-state dependence setings
1720#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyProcessorDefault) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1721 #undef CFG_ACPI_PSTATES_PSD_POLICY
1722 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyIndependent
1723#endif
1724
1725/*****************************************************************************
1726 *
1727 * Include the structure definitions for the defaults table structures
1728 *
1729 ****************************************************************************/
1730#include "Options.h"
1731#include "OptionCpuFamiliesInstall.h"
1732#include "OptionsHt.h"
1733#include "OptionHtInstall.h"
1734#include "OptionMemory.h"
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1735#include "OptionMemoryInstall.h"
1736#include "OptionMemoryRecovery.h"
1737#include "OptionMemoryRecoveryInstall.h"
1738#include "OptionCpuFeaturesInstall.h"
1739#include "OptionDmi.h"
1740#include "OptionDmiInstall.h"
1741#include "OptionPstate.h"
1742#include "OptionPstateInstall.h"
1743#include "OptionWhea.h"
1744#include "OptionWheaInstall.h"
1745#include "OptionCrat.h"
1746#include "OptionCratInstall.h"
1747#include "OptionCdit.h"
1748#include "OptionCditInstall.h"
1749#include "OptionSrat.h"
1750#include "OptionSratInstall.h"
1751#include "OptionSlit.h"
1752#include "OptionSlitInstall.h"
1753#include "OptionMultiSocket.h"
1754#include "OptionMultiSocketInstall.h"
1755#include "OptionIdsInstall.h"
1756#include "OptionGfxRecovery.h"
1757#include "OptionGfxRecoveryInstall.h"
1758#include "OptionGnb.h"
1759#include "OptionGnbInstall.h"
1760#include "OptionS3ScriptInstall.h"
1761#include "OptionFchInstall.h"
1762#include "OptionMmioMapInstall.h"
1763#include "OptionPrefetchModeInstall.h"
1764
1765
1766/*****************************************************************************
1767 *
1768 * Generate the output structures (defaults tables)
1769 *
1770 ****************************************************************************/
1771
1772FCH_PLATFORM_POLICY FchUserOptions = {
1773 CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress
1774 CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress
1775 CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress
1776 CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr
1777 CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr
1778 CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr
1779 CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr
1780 CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr
1781 CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr
1782 CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr
1783 CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase
1784 CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase
1785 CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress
1786 CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress
1787 0x780D1022ul,
1788 CFG_SMBUS_SSID, // CfgSmbusSsid
1789 CFG_IDE_SSID, // CfgIdeSsid
1790 CFG_SATA_AHCI_SSID, // CfgSataAhciSsid
1791 CFG_SATA_IDE_SSID, // CfgSataIdeSsid
1792 CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid
1793 CFG_SATA_RAID_SSID, // CfgSataRaidSsid
1794 CFG_EHCI_SSID, // CfgEhcidSsid
1795 CFG_OHCI_SSID, // CfgOhcidSsid
1796 CFG_LPC_SSID, // CfgLpcSsid
1797 CFG_SD_SSID, // CfgSdSsid
1798 CFG_XHCI_SSID, // CfgXhciSsid
1799 CFG_FCH_PORT80_BEHIND_PCIB, // CfgFchPort80BehindPcib
1800 CFG_FCH_ENABLE_ACPI_SLEEP_TRAP, // CfgFchEnableAcpiSleepTrap
1801 CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig
1802 CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present
1803 CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present
1804 CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present
1805 CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present
1806 CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug
1807 CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug
1808 CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug
1809 CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug
1810
1811 CFG_FCH_ESATA_PORT_BITMAP, // CfgFchEsataPortBitMap
1812 CFG_FCH_IR_PIN_CONTROL, // CfgFchIrPinControl
1813 CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl
1814 CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl
1815 CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]1816 CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl
1817 CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1818};
1819
1820BUILD_OPT_CFG UserOptions = {
1821 { // AGESA version string
1822 AGESA_CODE_SIGNATURE, // code header Signature
1823 AGESA_PACKAGE_STRING, // 16 character ID
1824 AGESA_VERSION_STRING, // 12 character version string
1825 0 // null string terminator
1826 },
1827 //Build Option Area
1828 OPTION_UDIMMS, //UDIMMS
1829 OPTION_RDIMMS, //RDIMMS
1830 OPTION_LRDIMMS, //LRDIMMS
1831 OPTION_ECC, //ECC
1832 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
1833 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
1834 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
1835 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
1836 OPTION_ONLINE_SPARE, //ONLINE_SPARE
1837 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
1838 OPTION_MULTISOCKET, //MULTISOCKET
1839 OPTION_ACPI_PSTATES, //ACPI_PSTATES
1840 OPTION_CPU_PSTATE_HPC_MODE, //High Preformace Computing (HPC) mode
1841 OPTION_CRAT, //CRAT
1842 OPTION_CDIT, //CDIT
1843 OPTION_SRAT, //SRAT
1844 OPTION_SLIT, //SLIT
1845 OPTION_WHEA, //WHEA
1846 OPTION_DMI, //DMI
1847 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
1848 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
1849
1850 //Build Configuration Area
1851 CFG_PCI_MMIO_BASE,
1852 CFG_PCI_MMIO_SIZE,
1853 {
1854 // CoreVrm
1855 {
1856 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
1857 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
1858 CFG_VRM_SLEW_RATE, // VrmSlewRate
1859 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
1860 CFG_VRM_MAXIMUM_CURRENT_LIMIT, // VrmMaximumCurrentLimit
1861 CFG_VRM_SVI_OCP_LEVEL // VrmSviOcpLevel
1862 },
1863 // NbVrm
1864 {
1865 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
1866 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
1867 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
1868 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
1869 CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT, // VrmNbMaximumCurrentLimit
1870 CFG_VRM_NB_SVI_OCP_LEVEL // VrmNbSviOcpLevel
1871 }
1872 },
1873 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
1874 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
1875 CFG_C1E_MODE, //C1eMode
1876 CFG_C1E_OPDATA, //C1ePlatformData
1877 CFG_C1E_OPDATA1, //C1ePlatformData1
1878 CFG_C1E_OPDATA2, //C1ePlatformData2
1879 CFG_C1E_OPDATA3, //C1ePlatformData3
1880 CFG_CSTATE_MODE, //CStateMode
1881 CFG_CSTATE_OPDATA, //CStatePlatformData
1882 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
1883 CFG_CPB_MODE, //CpbMode
1884 LOW_POWER_PSTATE_FOR_PROCHOT_AUTO, //Low power Pstate for PROCHOT, it's always set to 'AUTO'
1885 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
1886 {
1887 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
1888 CFG_USE_HT_ASSIST, // CfgUseHtAssist
1889 CFG_USE_ATM_MODE, // CfgUseAtmMode
1890 CFG_USE_NBR_CACHE, // CfgUseNbrCache
1891 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
1892 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
1893 // ADVANCED_PERFORMANCE_PROFILE
1894 {
1895 CFG_PERFORMANCE_HARDWARE_PREFETCHER, // Hardware prefetcher mode
1896 CFG_PERFORMANCE_SOFTWARE_PREFETCHES, // Software prefetcher mode
1897 CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode
1898 },
1899 CFG_PLATFORM_POWER_POLICY_MODE, // The platform's power policy mode.
1900 CFG_NB_PSTATES_SUPPORTED // The Nb-Pstates is supported or not
1901 },
1902 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
1903 CFG_AMD_PLATFORM_TYPE, // CfgAmdPlatformType
1904 CFG_AMD_POWER_CEILING, // CfgAmdPowerCeiling
1905 CFG_HTC_TEMPERATURE_LIMIT, // CfgHtcTemperatureLimit
1906 CFG_LHTC_TEMPERATURE_LIMIT, // CfgLhtcTemperatureLimit
1907
1908 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
1909 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
1910 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
1911 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
1912 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
1913 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
1914 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
1915 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
1916 CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb
1917 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
1918 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
1919 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
1920 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
1921 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
1922 CFG_ONLINE_SPARE, // CfgOnlineSpare
1923 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
1924 CFG_BANK_SWIZZLE, // CfgBankSwizzle
1925 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
1926 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
1927 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
1928 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
1929 CFG_USE_BURST_MODE, // CfgUseBurstMode
1930 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
1931 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
1932 CFG_ECC_REDIRECTION, // CfgEccRedirection
1933 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
1934 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
1935 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
1936 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
1937 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
1938 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
1939 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
1940 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
1941 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
1942 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
1943 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
1944 CFG_ACPI_PSTATES_PSD_POLICY, // CfgAcpiPstatesPsdPolicy
1945 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
1946 CFG_UMA_MODE, // CfgUmaMode
1947 CFG_UMA_SIZE, // CfgUmaSize
1948 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
1949 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
1950 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
1951 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
1952 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
1953 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
1954 CFG_ABM_SUPPORT, // CfgAbmSupport
1955 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
1956 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
1957 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
1958 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
1959 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
1960 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
1961 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
1962 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
1963 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
1964
1965 &FchUserOptions, // FchBldCfg
1966
1967 CFG_IOMMU_SUPPORT, // CfgIommuSupport
1968 CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe
1969 CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl
1970 CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon
1971 CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
1972 CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
1973 CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
1974 CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
1975 CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq
1976 CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue
1977 CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode
1978 {{
1979 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
1980 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
1981 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1982 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1983 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
1984 CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE, // CfgLvdsMiscControl
1985 }},
1986 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
1987 CFG_ENABLE_EXTERNAL_VREF, // CfgExternalVrefCtlFeature
1988 CFG_FORCE_TRAIN_MODE, // CfgForceTrainMode
1989 CFG_GNB_REMOTE_DISPLAY_SUPPORT, // CfgGnbRemoteDisplaySupport
1990 (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
1991 CFG_GNB_SYNCFLOOD_PIN_AS_NMI, // CfgGnbSyncFloodPinAsNmi
1992 CFG_IGPU_ENABLE_DISABLE_POLICY, // CfgIgpuEnableDisablePolicy
1993 CFG_GNB_THERMAL_SENSOR_CORRECTION, // CfgGnbSwTjOffset
1994 CFG_LVDS_MISC_VOLT_ADJUSTMENT, // CfgLvdsMiscVoltAdjustment
1995 {{
1996 0, // Reserved
1997 CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE, // CfgDisplayMiscControl.VbiosFastBootEn
1998 0, // Reserved
1999 }},
2000 CFG_DP_FIXED_VOLT_SWING, // CfgDpFixedVoltSwingType
2001 CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG, // CfgDimmTypeUsedInMixedConfig
2002 CFG_HYBRID_BOOST_ENABLE, // CfgHybridBoostEnable
2003 CFG_GNB_IOAPIC_ADDRESS, // CfgGnbIoapicAddress
2004 CFG_ENABLE_DATA_EYE, // CfgDataEyeEn
2005 CFG_DOCKED_TDP_HEADROOM, // CfgDockedTdpHeadroom
2006 CFG_DRAM_DOUBLE_REFRESH_RATE, // CfgDramDoubleRefreshRateEn
2007 0, //reserved...
2008};
2009
2010CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
2011{
2012 #if AGESA_ENTRY_INIT_RESET == TRUE
2013 { AMD_INIT_RESET,
2014 sizeof (AMD_RESET_PARAMS),
2015 (PF_AGESA_FUNCTION) AmdInitResetConstructor,
2016 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2017 AMD_INIT_RESET_HANDLE
2018 },
2019 #endif
2020
2021 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2022 { AMD_INIT_RECOVERY,
2023 sizeof (AMD_RECOVERY_PARAMS),
2024 (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
2025 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2026 AMD_INIT_POST_HANDLE
2027 },
2028 #endif
2029
2030 #if AGESA_ENTRY_INIT_EARLY == TRUE
2031 { AMD_INIT_EARLY,
2032 sizeof (AMD_EARLY_PARAMS),
2033 (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
2034 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2035 AMD_INIT_EARLY_HANDLE
2036 },
2037 #endif
2038
2039 #if AGESA_ENTRY_INIT_ENV == TRUE
2040 { AMD_INIT_ENV,
2041 sizeof (AMD_ENV_PARAMS),
2042 (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
2043 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2044 AMD_INIT_ENV_HANDLE
2045 },
2046 #endif
2047
2048 #if AGESA_ENTRY_INIT_LATE == TRUE
2049 { AMD_INIT_LATE,
2050 sizeof (AMD_LATE_PARAMS),
2051 (PF_AGESA_FUNCTION) AmdInitLateInitializer,
2052 (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
2053 AMD_INIT_LATE_HANDLE
2054 },
2055 #endif
2056
2057 #if AGESA_ENTRY_INIT_MID == TRUE
2058 { AMD_INIT_MID,
2059 sizeof (AMD_MID_PARAMS),
2060 (PF_AGESA_FUNCTION) AmdInitMidInitializer,
2061 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2062 AMD_INIT_MID_HANDLE
2063 },
2064 #endif
2065
2066 #if AGESA_ENTRY_INIT_POST == TRUE
2067 { AMD_INIT_POST,
2068 sizeof (AMD_POST_PARAMS),
2069 (PF_AGESA_FUNCTION) AmdInitPostInitializer,
2070 (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
2071 AMD_INIT_POST_HANDLE
2072 },
2073 #endif
2074
2075 #if AGESA_ENTRY_INIT_RESUME == TRUE
2076 { AMD_INIT_RESUME,
2077 sizeof (AMD_RESUME_PARAMS),
2078 (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
2079 (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
2080 AMD_INIT_RESUME_HANDLE
2081 },
2082 #endif
2083
2084 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2085 { AMD_S3LATE_RESTORE,
2086 sizeof (AMD_S3LATE_PARAMS),
2087 (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
2088 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2089 AMD_S3_LATE_RESTORE_HANDLE
2090 },
2091 #endif
2092
2093 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2094 { AMD_S3_SAVE,
2095 sizeof (AMD_S3SAVE_PARAMS),
2096 (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
2097 (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
2098 AMD_S3_SAVE_HANDLE
2099 },
2100 #endif
2101
2102 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2103 { AMD_LATE_RUN_AP_TASK,
2104 sizeof (AP_EXE_PARAMS),
2105 (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
2106 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2107 AMD_LATE_RUN_AP_TASK_HANDLE
2108 },
2109 #endif
2110 { 0, 0, NULL, NULL, 0 }
2111};
2112
2113CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
2114
2115CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
2116{
2117 { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
2118 { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
2119
2120 #if AGESA_ENTRY_INIT_RESET == TRUE
2121 { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
2122 #endif
2123
2124 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2125 { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
2126 #endif
2127
2128 #if AGESA_ENTRY_INIT_EARLY == TRUE
2129 { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
2130 #endif
2131
2132 #if AGESA_ENTRY_INIT_POST == TRUE
2133 { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
2134 #if OPTION_DATA_EYE == TRUE
2135 { AMD_GET_2D_DATA_EYE, (IMAGE_ENTRY)AmdGet2DDataEye },
2136 #endif
2137 #endif
2138
2139 #if AGESA_ENTRY_INIT_ENV == TRUE
2140 { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
2141 #endif
2142
2143 #if AGESA_ENTRY_INIT_MID == TRUE
2144 { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
2145 #endif
2146
2147 #if AGESA_ENTRY_INIT_LATE == TRUE
2148 { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
2149 #endif
2150
2151 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2152 { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
2153 #endif
2154
2155 #if AGESA_ENTRY_INIT_RESUME == TRUE
2156 { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
2157 #endif
2158
2159 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2160 { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
2161 #endif
2162
2163 #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
2164 { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
2165 { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
2166 { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
2167 { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
2168 { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
2169 { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
2170 #endif
2171
2172 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2173 { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
2174 #endif
2175 { 0, NULL }
2176};
2177
2178CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
2179{
2180 IDS_LATE_RUN_AP_TASK
2181 // Get DMI info
2182 CPU_DMI_AP_GET_TYPE4_TYPE7
2183 // Probe filter enable
2184 L3_FEAT_AP_DISABLE_CACHE
2185 L3_FEAT_AP_ENABLE_CACHE
2186 // Cpu Prefetch Mode
2187 CPU_PREFETCH_MODE_AP_TASK
2188 { 0, NULL }
2189};
2190
2191#if AGESA_ENTRY_INIT_EARLY == TRUE
2192 #if IDSOPT_IDS_ENABLED == TRUE
2193 #if IDSOPT_TRACING_ENABLED == TRUE
2194 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
2195 CONST CHAR8 *BldOptDebugOutput[] = {
2196 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
2197 //Build Option Area
2198 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
2199 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
2200 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
2201 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
2202 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
2203 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
2204 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
2205 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
2206 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
2207 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
2208 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
2209 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
2210 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
2211 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
2212 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
2213 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
2214 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
2215 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
2216
2217 //Build Configuration Area
2218 // CoreVrm
2219 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
2220 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
2221 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
2222 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
2223 MAKE_DBG_STR (\nVrmMaximumCurrentLimit, CFG_VRM_MAXIMUM_CURRENT_LIMIT)
2224 MAKE_DBG_STR (\nVrmSviOcpLevel, CFG_VRM_SVI_OCP_LEVEL)
2225 // NbVrm
2226 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
2227 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
2228 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
2229 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
2230 MAKE_DBG_STR (\nNbVrmMaximumCurrentLimit, CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT),
2231 MAKE_DBG_STR (\nNbVrmSviOcpLevel, CFG_VRM_NB_SVI_OCP_LEVEL)
2232
2233 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
2234 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
2235 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
2236 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
2237 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
2238 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
2239 MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3)
2240 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
2241 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
2242 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
2243 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
2244 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
2245
2246 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
2247 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
2248 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
2249 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
2250 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2251 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
2252
2253 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
2254
2255 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2256 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2257 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2258 MAKE_DBG_STR (\nPowerCeiling , CFG_AMD_POWER_CEILING),
2259 MAKE_DBG_STR (\nHtcTempLimit , CFG_HTC_TEMPERATURE_LIMIT)
2260 MAKE_DBG_STR (\nLhtcTempLimit , CFG_LHTC_TEMPERATURE_LIMIT)
2261
2262 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2263 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2264 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2265
2266 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2267 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2268 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2269 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2270 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2271 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2272 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2273 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2274 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2275 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2276 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2277
2278 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2279 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2280 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2281 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2282 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2283 MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
2284 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2285 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2286 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2287
2288 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2289 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2290 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2291 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2292
2293 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2294 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2295 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2296 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2297 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2298 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2299 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2300 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2301 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2302 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2303 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2304
2305 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2306 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2307 MAKE_DBG_STR (\nAcpiPstatesPsdPolicy , CFG_ACPI_PSTATES_PSD_POLICY)
2308
2309 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2310
2311 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2312 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2313 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2314 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2315 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2316 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2317 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2318 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2319 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2320 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID)
2321 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID)
2322 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID)
2323 MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT)
2324 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM)
2325 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
2326 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
2327 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
2328 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
2329 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
2330 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
2331 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
2332 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
2333 MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
2334 MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
2335 MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE),
2336 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
2337 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
2338 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
2339 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
2340 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
2341 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
2342 MAKE_DBG_STR (\nCfgExtVref , CFG_ENABLE_EXTERNAL_VREF),
2343 MAKE_DBG_STR (\nCfgForceTrainMode , CFG_FORCE_TRAIN_MODE),
2344 MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport , CFG_GNB_REMOTE_DISPLAY_CONFIG),
2345 MAKE_DBG_STR (\nCfgIvrsExclusionRangeList , CFG_IOMMU_EXCLUSION_RANGE_LIST),
2346 MAKE_DBG_STR (\nCfgGnbSyncFloodPinAsNmi , CFG_GNB_SYNCFLOOD_PIN_AS_NMI),
2347 MAKE_DBG_STR (\nCfgIgpuEnableDisablePolicy , CFG_IGPU_ENABLE_DISABLE_POLICY),
2348 MAKE_DBG_STR (\nCfgGnbSwTjOffset , CFG_GNB_THERMAL_SENSOR_CORRECTION),
2349 MAKE_DBG_STR (\nCfgDisplayMiscControl.VbiosFastBootEn , CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE),
2350 MAKE_DBG_STR (\nCfgDimmTypeUsedInMixedConfig , CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG),
2351 MAKE_DBG_STR (\nCfgDataEyeEn , CFG_ENABLE_DATA_EYE),
2352 MAKE_DBG_STR (\nCfgDramDoubleRefreshRateEn , CFG_DRAM_DOUBLE_REFRESH_RATE),
2353 #endif
2354 NULL
2355 };
2356 #endif
2357 #endif
2358#endif
2359
2360// Needed for floating point support, linker expects this symbol to be defined.
2361#if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
2362 CONST INT32 _fltused = 0;
2363#endif
2364