blob: a3d0a2cb18a367c3add7c1554d11a318e2c843da [file] [log] [blame]
Kane Chen01ebc742019-08-23 12:03:05 +08001/*
2 * This file is part of the coreboot project.
3 *
Kane Chen01ebc742019-08-23 12:03:05 +08004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <device/pci.h>
16#include <device/pci_ids.h>
17#include <console/console.h>
Kyösti Mälkki32d47eb2019-09-28 00:00:30 +030018#include <intelblocks/cfg.h>
Kane Chen01ebc742019-08-23 12:03:05 +080019#include <intelblocks/mmc.h>
20
21static int mmc_write_dll_reg(void *bar, uint32_t reg, uint32_t val)
22{
23 int ret = 0;
24 if (val) {
25 write32(bar + reg, val);
26 ret = 1;
27 }
28 return ret;
29}
30
31int set_mmc_dll(void *bar)
32{
33 const struct soc_intel_common_config *common_config;
34 const struct mmc_dll_params *dll_params;
35 int override = 0;
36
37 common_config = chip_get_common_soc_structure();
38 dll_params = &common_config->emmc_dll;
39
40 override |= mmc_write_dll_reg(bar, EMMC_TX_CMD_CNTL_OFFSET,
41 dll_params->emmc_tx_cmd_cntl);
42
43 override |= mmc_write_dll_reg(bar, EMMC_TX_DATA_CNTL1_OFFSET,
44 dll_params->emmc_tx_data_cntl1);
45
46 override |= mmc_write_dll_reg(bar, EMMC_TX_DATA_CNTL2_OFFSET,
47 dll_params->emmc_tx_data_cntl2);
48
49 override |= mmc_write_dll_reg(bar, EMMC_RX_CMD_DATA_CNTL1_OFFSET,
50 dll_params->emmc_rx_cmd_data_cntl1);
51
52 override |= mmc_write_dll_reg(bar, EMMC_RX_STROBE_CNTL_OFFSET,
53 dll_params->emmc_rx_strobe_cntl);
54
55 override |= mmc_write_dll_reg(bar, EMMC_RX_CMD_DATA_CNTL2_OFFSET,
56 dll_params->emmc_rx_cmd_data_cntl2);
57
58 if (override == 0) {
59 printk(BIOS_INFO, "Skip Emmc dll value programming\n");
60 return -1;
61 }
62
63 return 0;
64}
65
66static void mmc_soc_init(struct device *dev)
67{
68 const struct resource *res;
69
70 if (!CONFIG(SOC_INTEL_COMMON_MMC_OVERRIDE))
71 return;
72
73 res = find_resource(dev, PCI_BASE_ADDRESS_0);
74 set_mmc_dll((void *)(uintptr_t)(res->base));
75}
76
77static struct device_operations dev_ops = {
78 .read_resources = pci_dev_read_resources,
79 .set_resources = pci_dev_set_resources,
80 .enable_resources = pci_dev_enable_resources,
81 .init = mmc_soc_init,
82 .ops_pci = &pci_dev_ops_pci,
83};
84
85static const unsigned short pci_device_ids[] = {
86 PCI_DEVICE_ID_INTEL_CMP_EMMC,
Meera Ravindranath3f4af0d2020-02-12 16:01:22 +053087 PCI_DEVICE_ID_INTEL_JSP_EMMC,
Kane Chen01ebc742019-08-23 12:03:05 +080088 0
89};
90
91static const struct pci_driver pch_sd __pci_driver = {
92 .ops = &dev_ops,
93 .vendor = PCI_VENDOR_ID_INTEL,
94 .devices = pci_device_ids,
95};