Felix Held | 6abaccf | 2022-01-10 20:55:01 +0100 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * |
| 3 | * Copyright (c) 2020, Advanced Micro Devices, Inc. |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions are met: |
| 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in the |
| 12 | * documentation and/or other materials provided with the distribution. |
| 13 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 14 | * its contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 19 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 20 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 21 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 22 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 23 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 24 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 26 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | ***************************************************************************/ |
| 29 | |
| 30 | #ifndef _BL_SYSCALL_PUBLIC_H_ |
| 31 | #define _BL_SYSCALL_PUBLIC_H_ |
| 32 | |
| 33 | #include <stdint.h> |
| 34 | |
Karthikeyan Ramasubramanian | 0fa0a3e | 2022-04-18 17:07:33 -0600 | [diff] [blame] | 35 | #define SVC_EXIT 0x00 |
| 36 | #define SVC_ENTER 0x02 |
| 37 | #define SVC_VERSTAGE_CMD 0x3A |
| 38 | |
| 39 | enum verstage_cmd_id { |
| 40 | CMD_SHA = 1, |
| 41 | CMD_MODEXP, |
| 42 | CMD_DEBUG_PRINT, |
| 43 | CMD_DEBUG_PRINT_EX, |
| 44 | CMD_UPDATE_PSP_BIOS_DIR, |
| 45 | CMD_GET_SPI_INFO, |
| 46 | CMD_MAP_SPIROM_DEVICE, |
| 47 | CMD_UNMAP_SPIROM_DEVICE, |
| 48 | CMD_READ_TIMER_VAL, |
| 49 | CMD_DELAY_IN_MICRO_SECONDS, |
| 50 | CMD_RESET_SYSTEM, |
| 51 | CMD_GET_BOOT_MODE, |
| 52 | CMD_COPY_DATA_FROM_UAPP, |
| 53 | CMD_MAP_FCH_IO_DEVICE, |
| 54 | CMD_UNMAP_FCH_IO_DEVICE, |
| 55 | CMD_CCP_DMA, |
| 56 | CMD_SET_PLATFORM_BOOT_MODE, |
Karthikeyan Ramasubramanian | 35aa435 | 2022-08-25 12:52:13 -0600 | [diff] [blame] | 57 | CMD_SET_FW_HASH_TABLE, |
Karthikeyan Ramasubramanian | 7b49d1b | 2022-12-05 14:49:38 -0700 | [diff] [blame] | 58 | CMD_GET_PREV_BOOT_STATUS, |
Karthikeyan Ramasubramanian | 8420ccc | 2022-12-22 12:01:01 -0700 | [diff] [blame] | 59 | CMD_GET_HSP_SECURE_STATE, |
Martin Roth | 72c38c9 | 2023-01-11 19:12:20 -0700 | [diff] [blame] | 60 | CMD_WRITE_POSTCODE, |
Karthikeyan Ramasubramanian | 0fa0a3e | 2022-04-18 17:07:33 -0600 | [diff] [blame] | 61 | }; |
Felix Held | 6abaccf | 2022-01-10 20:55:01 +0100 | [diff] [blame] | 62 | |
| 63 | struct mod_exp_params { |
| 64 | char *pExponent; // Exponent address |
| 65 | unsigned int ExpSize; // Exponent size in bytes |
| 66 | char *pModulus; // Modulus address |
| 67 | unsigned int ModulusSize; // Modulus size in bytes |
| 68 | char *pMessage; // Message address, same size as ModulusSize |
| 69 | char *pOutput; // Output address; Must be big enough to hold the |
| 70 | // data of ModulusSize |
| 71 | }; |
| 72 | |
| 73 | enum psp_boot_mode { |
| 74 | PSP_BOOT_MODE_S0 = 0x0, |
| 75 | PSP_BOOT_MODE_S0i3_RESUME = 0x1, |
| 76 | PSP_BOOT_MODE_S3_RESUME = 0x2, |
| 77 | PSP_BOOT_MODE_S4 = 0x3, |
| 78 | PSP_BOOT_MODE_S5_COLD = 0x4, |
| 79 | PSP_BOOT_MODE_S5_WARM = 0x5, |
| 80 | }; |
| 81 | |
| 82 | enum reset_type |
| 83 | { |
| 84 | RESET_TYPE_COLD = 0, |
| 85 | RESET_TYPE_WARM = 1, |
| 86 | RESET_TYPE_MAX = 2, |
| 87 | }; |
| 88 | |
| 89 | enum fch_io_device { |
| 90 | FCH_IO_DEVICE_SPI, |
| 91 | FCH_IO_DEVICE_I2C, |
| 92 | FCH_IO_DEVICE_GPIO, |
| 93 | FCH_IO_DEVICE_ESPI, |
| 94 | FCH_IO_DEVICE_IOMUX, |
| 95 | FCH_IO_DEVICE_MISC, |
| 96 | FCH_IO_DEVICE_AOAC, |
| 97 | FCH_IO_DEVICE_IOPORT, |
Felix Held | 6abaccf | 2022-01-10 20:55:01 +0100 | [diff] [blame] | 98 | FCH_IO_DEVICE_END, |
| 99 | }; |
| 100 | |
| 101 | enum fch_i2c_controller_id { |
| 102 | FCH_I2C_CONTROLLER_ID_0 = 0, |
| 103 | FCH_I2C_CONTROLLER_ID_1 = 1, |
| 104 | FCH_I2C_CONTROLLER_ID_2 = 2, |
| 105 | FCH_I2C_CONTROLLER_ID_3 = 3, |
| 106 | FCH_I2C_CONTROLLER_ID_MAX, |
| 107 | }; |
| 108 | |
| 109 | struct spirom_info { |
| 110 | void *SpiBiosSysHubBase; |
| 111 | void *SpiBiosSmnBase; |
| 112 | uint32_t SpiBiosSize; |
| 113 | }; |
| 114 | |
| 115 | enum psp_timer_type { |
| 116 | PSP_TIMER_TYPE_CHRONO = 0, |
| 117 | PSP_TIMER_TYPE_SECURE_RTC = 1, |
| 118 | PSP_TIMER_TYPE_MAX = 2, |
| 119 | }; |
| 120 | |
| 121 | /* SHA types same as ccp SHA type in crypto.h */ |
| 122 | enum sha_type { |
| 123 | SHA_TYPE_256, |
| 124 | SHA_TYPE_384 |
| 125 | }; |
| 126 | |
| 127 | /* All SHA operation supported */ |
| 128 | enum sha_operation_mode { |
| 129 | SHA_GENERIC |
| 130 | }; |
| 131 | |
| 132 | /* SHA Supported Data Structures */ |
| 133 | struct sha_generic_data { |
| 134 | enum sha_type SHAType; |
| 135 | uint8_t *Data; |
| 136 | uint32_t DataLen; |
| 137 | uint32_t DataMemType; |
| 138 | uint8_t *Digest; |
| 139 | uint32_t DigestLen; |
| 140 | uint8_t *IntermediateDigest; |
| 141 | uint32_t IntermediateMsgLen; |
| 142 | uint32_t Init; |
| 143 | uint32_t Eom; |
| 144 | }; |
| 145 | |
| 146 | /* |
Karthikeyan Ramasubramanian | 0fa0a3e | 2022-04-18 17:07:33 -0600 | [diff] [blame] | 147 | * This is state that PSP manages internally. |
| 148 | * We only report BOOT_MODE_DEVELOPER or BOOT_MODE_NORMAL in verstage. |
| 149 | */ |
| 150 | enum chrome_platform_boot_mode |
| 151 | { |
| 152 | NON_CHROME_BOOK_BOOT_MODE = 0x0, |
| 153 | CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1, |
| 154 | CHROME_BOOK_BOOT_MODE_NORMAL = 0x2, |
| 155 | CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3, |
| 156 | CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check |
| 157 | }; |
| 158 | |
Karthikeyan Ramasubramanian | 35aa435 | 2022-08-25 12:52:13 -0600 | [diff] [blame] | 159 | struct psp_fw_entry_hash_256 { |
| 160 | uint16_t fw_type; |
| 161 | uint16_t sub_type; |
| 162 | uint8_t sha[32]; |
| 163 | } __packed; |
| 164 | |
| 165 | struct psp_fw_entry_hash_384 { |
| 166 | uint16_t fw_type; |
| 167 | uint16_t sub_type; |
| 168 | uint8_t sha[48]; |
| 169 | } __packed; |
| 170 | |
| 171 | struct psp_fw_hash_table { |
| 172 | uint16_t version; // Version of psp_fw_hash_table, Start with 0. |
| 173 | uint16_t no_of_entries_256; |
| 174 | uint16_t no_of_entries_384; |
| 175 | struct psp_fw_entry_hash_256 *fw_hash_256; |
| 176 | struct psp_fw_entry_hash_384 *fw_hash_384; |
| 177 | } __packed; |
| 178 | |
Karthikeyan Ramasubramanian | 0fa0a3e | 2022-04-18 17:07:33 -0600 | [diff] [blame] | 179 | /* |
Felix Held | 6abaccf | 2022-01-10 20:55:01 +0100 | [diff] [blame] | 180 | * Exit to the main Boot Loader. This does not return back to user application. |
| 181 | * |
| 182 | * Parameters: |
| 183 | * status - either Ok or error code defined by AGESA |
| 184 | */ |
| 185 | void svc_exit(uint32_t status); |
| 186 | |
| 187 | /* Print debug message into serial console. |
| 188 | * |
| 189 | * Parameters: |
| 190 | * string - null-terminated string |
| 191 | */ |
| 192 | void svc_debug_print(const char *string); |
| 193 | |
| 194 | /* Print 4 DWORD values in hex to serial console |
| 195 | * |
| 196 | * Parameters: |
| 197 | * dword0...dword3 - 32-bit DWORD to print |
| 198 | */ |
| 199 | void svc_debug_print_ex(uint32_t dword0, |
| 200 | uint32_t dword1, uint32_t dword2, uint32_t dword3); |
| 201 | |
| 202 | /* Description - Returns the current boot mode from the enum psp_boot_mode found in |
| 203 | * bl_public.h. |
| 204 | * |
| 205 | * Inputs - boot_mode - Output parameter passed in R0 |
| 206 | * |
| 207 | * Outputs - The boot mode in boot_mode. |
| 208 | * See Return Values. |
| 209 | * |
| 210 | * Return Values - BL_OK |
| 211 | * BL_ERR_NULL_PTR |
| 212 | * Other BL_ERRORs lofted up from called functions |
| 213 | */ |
| 214 | uint32_t svc_get_boot_mode(uint32_t *boot_mode); |
| 215 | |
| 216 | /* Add delay in micro seconds |
| 217 | * |
| 218 | * Parameters: |
| 219 | * delay - required delay value in microseconds |
| 220 | * |
| 221 | * Return value: NONE |
| 222 | */ |
| 223 | void svc_delay_in_usec(uint32_t delay); |
| 224 | |
| 225 | /* Get the SPI-ROM information |
| 226 | * |
| 227 | * Parameters: |
| 228 | * spi_rom_iInfo - SPI-ROM information |
| 229 | * |
| 230 | * Return value: BL_OK or error code |
| 231 | */ |
| 232 | uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info); |
| 233 | |
| 234 | /* Map the FCH IO device register space (SPI/I2C/GPIO/eSPI/etc...) |
| 235 | * |
| 236 | * Parameters: |
| 237 | * io_device - ID for respective FCH IO controller register space to be mapped |
| 238 | * arg1 - Based on IODevice ID, interpretation of this argument changes. |
| 239 | * arg2 - Based on IODevice ID, interpretation of this argument changes. |
| 240 | * io_device_axi_addr - AXI address for respective FCH IO device register space |
| 241 | * |
| 242 | * Return value: BL_OK or error code |
| 243 | */ |
| 244 | uint32_t svc_map_fch_dev(enum fch_io_device io_device, |
| 245 | uint32_t arg1, uint32_t arg2, void **io_device_axi_addr); |
| 246 | |
| 247 | /* Unmap the FCH IO device register space mapped earlier using Svc_MapFchIODevice() |
| 248 | * |
| 249 | * Parameters: |
| 250 | * io_device - ID for respective FCH IO controller register space to be unmapped |
| 251 | * io_device_addr - AXI address for respective FCH IO device register space |
| 252 | * |
| 253 | * Return value: BL_OK or error code |
| 254 | */ |
| 255 | uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, |
| 256 | void *io_device_axi_addr); |
| 257 | |
| 258 | /* Map the SPIROM FLASH device address space |
| 259 | * |
| 260 | * Parameters: |
| 261 | * SpiRomAddr - Address in SPIROM tobe mapped (SMN based) |
| 262 | * size - Size to be mapped |
| 263 | * pSpiRomAddrAxi - Mapped address in AXI space |
| 264 | * |
| 265 | * Return value: BL_OK or error code |
| 266 | */ |
| 267 | uint32_t svc_map_spi_rom(void *spi_rom_addr, |
| 268 | uint32_t size, void **spi_rom_axi_addr); |
| 269 | |
| 270 | /* Unmap the SPIROM FLASH device address space mapped earlier using Svc_MapSpiRomDevice() |
| 271 | * |
| 272 | * Parameters: |
| 273 | * pSpiRomAddrAxi - Address in AXI address space previously mapped |
| 274 | * |
| 275 | * Return value: BL_OK or error code |
| 276 | */ |
| 277 | uint32_t svc_unmap_spi_rom(void *spi_rom_addr); |
| 278 | |
| 279 | /* Updates the offset at which PSP or BIOS Directory can be found in the |
| 280 | * SPI flash |
| 281 | * |
| 282 | * Parameters: |
| 283 | * psp_dir_offset - [in/out] Offset at which PSP Directory can be |
| 284 | * found in the SPI Flash. Same pointer is used |
| 285 | * to return the offset in case of GET operation |
| 286 | * bios_dir_offset - [in/out] Offset at which BIOS Directory can be |
| 287 | * found in the SPI Flash. Same pointer is used |
| 288 | * to return the offset in case of GET operation |
| 289 | * |
| 290 | * Return value: BL_OK or error code |
| 291 | */ |
| 292 | uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, |
| 293 | uint32_t *bios_dir_offset); |
| 294 | |
| 295 | /* Copies the data that is shared by verstage to the PSP BL owned memory |
| 296 | * |
| 297 | * Parameters: |
| 298 | * address - Address in UAPP controlled/owned memory |
| 299 | * size - Total size of memory to copy (max 16Kbytes) |
| 300 | */ |
| 301 | uint32_t svc_save_uapp_data(void *address, uint32_t size); |
| 302 | |
| 303 | /* |
| 304 | * Read timer raw (currently CHRONO and RTC) value |
| 305 | * |
| 306 | * Parameters: |
| 307 | * type - [in] Type of timer UAPP would like to read from |
| 308 | * (currently CHRONO and RTC) |
| 309 | * counter_value - [out] return the raw counter value read from |
| 310 | * RTC or CHRONO_LO/HI counter register |
| 311 | -----------------------------------------------------------------------------*/ |
| 312 | uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value); |
| 313 | |
| 314 | /* |
| 315 | * Reset the system |
| 316 | * |
| 317 | * Parameters: |
| 318 | * reset_type - Cold or Warm reset |
| 319 | */ |
| 320 | uint32_t svc_reset_system(enum reset_type reset_type); |
| 321 | |
| 322 | /* |
| 323 | * Write postcode to Port-80 |
| 324 | * |
| 325 | * Parameters: |
| 326 | * postcode - Postcode value to be written on port-80h |
| 327 | */ |
| 328 | uint32_t svc_write_postcode(uint32_t postcode); |
| 329 | |
| 330 | /* |
| 331 | * Generic SHA call for SHA, SHA_OTP, SHA_HMAC |
| 332 | */ |
| 333 | uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode); |
| 334 | |
| 335 | /* |
| 336 | * Calculate ModEx |
| 337 | * |
| 338 | * Parameters: |
| 339 | * mod_exp_param - ModExp parameters |
| 340 | * |
| 341 | * Return value: BL_OK or error code |
| 342 | */ |
| 343 | uint32_t svc_modexp(struct mod_exp_params *mod_exp_param); |
| 344 | |
| 345 | /* |
| 346 | * Copies the data from source to destination using ccp |
| 347 | * |
| 348 | * Parameters: |
| 349 | * Source Address - SPI ROM offset |
| 350 | * Destination Address - Address in Verstage memory |
| 351 | * Size - Total size to copy |
| 352 | * |
| 353 | * Return value: BL_OK or error code |
| 354 | */ |
| 355 | uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size); |
| 356 | |
Karthikeyan Ramasubramanian | 0fa0a3e | 2022-04-18 17:07:33 -0600 | [diff] [blame] | 357 | /* |
| 358 | * Get the Platform boot mode from verstage. Normal or developer |
| 359 | * |
| 360 | * Parameters: |
| 361 | * - boot mode |
| 362 | -----------------------------------------------------------------------------*/ |
| 363 | uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode); |
| 364 | |
Karthikeyan Ramasubramanian | 35aa435 | 2022-08-25 12:52:13 -0600 | [diff] [blame] | 365 | /* |
| 366 | * Set the PSP FW hash table. |
| 367 | * |
| 368 | * Parameters: |
| 369 | * - hash_table - Table of hash for each PSP binary signed against SoC chain of trust |
| 370 | * |
| 371 | * Return value: BL_OK or error code |
| 372 | */ |
| 373 | uint32_t svc_set_fw_hash_table(struct psp_fw_hash_table *hash_table); |
| 374 | |
Karthikeyan Ramasubramanian | 7b49d1b | 2022-12-05 14:49:38 -0700 | [diff] [blame] | 375 | /* Get the previous boot status. |
| 376 | * |
| 377 | * Parameters: |
| 378 | * - boot_status - Address where the boot status is read into |
| 379 | * |
| 380 | * Return value: BL_OK or error code |
| 381 | */ |
| 382 | uint32_t svc_get_prev_boot_status(uint32_t *boot_status); |
| 383 | |
Karthikeyan Ramasubramanian | 8420ccc | 2022-12-22 12:01:01 -0700 | [diff] [blame] | 384 | /* Get HSP Secure state |
| 385 | * |
| 386 | * Parameters: |
| 387 | * - hsp_secure_state - Address where the state info is read into |
| 388 | * |
| 389 | * Return value: BL_OK or error code |
| 390 | */ |
| 391 | uint32_t svc_get_hsp_secure_state(uint32_t *hsp_secure_state); |
| 392 | |
Felix Held | 6abaccf | 2022-01-10 20:55:01 +0100 | [diff] [blame] | 393 | /* C entry point for the Bootloader Userspace Application */ |
| 394 | void Main(void); |
| 395 | |
| 396 | #endif /* _BL_SYSCALL__PUBLIC_H_ */ |