Timothy Pearson | 04cf449 | 2015-09-05 17:38:09 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: Dave Airlie <airlied@redhat.com> |
| 28 | */ |
| 29 | |
| 30 | #define COREBOOT_AST_FAILOVER_TIMEOUT 10000000 |
| 31 | |
| 32 | #include "ast_drv.h" |
| 33 | |
| 34 | #include "ast_dram_tables.h" |
| 35 | |
| 36 | static void ast_init_dram_2300(struct drm_device *dev); |
| 37 | |
| 38 | void ast_enable_vga(struct drm_device *dev) |
| 39 | { |
| 40 | struct ast_private *ast = dev->dev_private; |
| 41 | |
| 42 | ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); |
| 43 | ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); |
| 44 | } |
| 45 | |
| 46 | void ast_enable_mmio(struct drm_device *dev) |
| 47 | { |
| 48 | struct ast_private *ast = dev->dev_private; |
| 49 | |
| 50 | ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); |
| 51 | } |
| 52 | |
| 53 | |
| 54 | bool ast_is_vga_enabled(struct drm_device *dev) |
| 55 | { |
| 56 | struct ast_private *ast = dev->dev_private; |
| 57 | u8 ch; |
| 58 | |
| 59 | if (ast->chip == AST1180) { |
| 60 | /* TODO 1180 */ |
| 61 | } else { |
| 62 | ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); |
| 63 | if (ch) { |
| 64 | ast_open_key(ast); |
| 65 | ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff); |
| 66 | return ch & 0x04; |
| 67 | } |
| 68 | } |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; |
| 73 | static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff }; |
| 74 | static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff }; |
| 75 | |
| 76 | static void |
| 77 | ast_set_def_ext_reg(struct drm_device *dev) |
| 78 | { |
| 79 | struct ast_private *ast = dev->dev_private; |
| 80 | u8 i, index, reg; |
| 81 | uint32_t data; |
| 82 | const u8 *ext_reg_info; |
| 83 | |
| 84 | pci_read_config_dword(ast->dev->pdev, 0x08, &data); |
| 85 | uint8_t revision = data & 0xff; |
| 86 | |
| 87 | /* reset scratch */ |
| 88 | for (i = 0x81; i <= 0x8f; i++) |
| 89 | ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); |
| 90 | |
| 91 | if (ast->chip == AST2300 || ast->chip == AST2400) { |
| 92 | if (revision >= 0x20) |
| 93 | ext_reg_info = extreginfo_ast2300; |
| 94 | else |
| 95 | ext_reg_info = extreginfo_ast2300a0; |
| 96 | } else |
| 97 | ext_reg_info = extreginfo; |
| 98 | |
| 99 | index = 0xa0; |
| 100 | while (*ext_reg_info != 0xff) { |
| 101 | ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); |
| 102 | index++; |
| 103 | ext_reg_info++; |
| 104 | } |
| 105 | |
| 106 | /* disable standard IO/MEM decode if secondary */ |
| 107 | /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */ |
| 108 | |
| 109 | /* Set Ext. Default */ |
| 110 | ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); |
| 111 | ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); |
| 112 | |
| 113 | /* Enable RAMDAC for A1 */ |
| 114 | reg = 0x04; |
| 115 | if (ast->chip == AST2300 || ast->chip == AST2400) |
| 116 | reg |= 0x20; |
| 117 | ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); |
| 118 | } |
| 119 | |
| 120 | u32 ast_mindwm(struct ast_private *ast, u32 r) |
| 121 | { |
| 122 | uint32_t timeout; |
| 123 | uint32_t data; |
| 124 | |
| 125 | ast_write32(ast, 0xf004, r & 0xffff0000); |
| 126 | ast_write32(ast, 0xf000, 0x1); |
| 127 | |
| 128 | timeout = 0; |
| 129 | do { |
| 130 | data = ast_read32(ast, 0xf004) & 0xffff0000; |
| 131 | timeout++; |
| 132 | } while ((data != (r & 0xffff0000)) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 133 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 134 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 135 | return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); |
| 136 | } |
| 137 | |
| 138 | void ast_moutdwm(struct ast_private *ast, u32 r, u32 v) |
| 139 | { |
| 140 | uint32_t timeout; |
| 141 | uint32_t data; |
| 142 | |
| 143 | ast_write32(ast, 0xf004, r & 0xffff0000); |
| 144 | ast_write32(ast, 0xf000, 0x1); |
| 145 | timeout = 0; |
| 146 | do { |
| 147 | data = ast_read32(ast, 0xf004) & 0xffff0000; |
| 148 | timeout++; |
| 149 | } while ((data != (r & 0xffff0000)) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 150 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 151 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 152 | ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); |
| 153 | } |
| 154 | |
| 155 | /* |
| 156 | * AST2100/2150 DLL CBR Setting |
| 157 | */ |
| 158 | #define CBR_SIZE_AST2150 ((16 << 10) - 1) |
| 159 | #define CBR_PASSNUM_AST2150 5 |
| 160 | #define CBR_THRESHOLD_AST2150 10 |
| 161 | #define CBR_THRESHOLD2_AST2150 10 |
| 162 | #define TIMEOUT_AST2150 5000000 |
| 163 | |
| 164 | #define CBR_PATNUM_AST2150 8 |
| 165 | |
| 166 | static const u32 pattern_AST2150[14] = { |
| 167 | 0xFF00FF00, |
| 168 | 0xCC33CC33, |
| 169 | 0xAA55AA55, |
| 170 | 0xFFFE0001, |
| 171 | 0x683501FE, |
| 172 | 0x0F1929B0, |
| 173 | 0x2D0B4346, |
| 174 | 0x60767F02, |
| 175 | 0x6FBE36A6, |
| 176 | 0x3A253035, |
| 177 | 0x3019686D, |
| 178 | 0x41C6167E, |
| 179 | 0x620152BF, |
| 180 | 0x20F050E0 |
| 181 | }; |
| 182 | |
| 183 | static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen) |
| 184 | { |
| 185 | u32 data, timeout; |
| 186 | |
| 187 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 188 | ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); |
| 189 | timeout = 0; |
| 190 | do { |
| 191 | data = ast_mindwm(ast, 0x1e6e0070) & 0x40; |
| 192 | if (++timeout > TIMEOUT_AST2150) { |
| 193 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 194 | return 0xffffffff; |
| 195 | } |
| 196 | } while (!data); |
| 197 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 198 | ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); |
| 199 | timeout = 0; |
| 200 | do { |
| 201 | data = ast_mindwm(ast, 0x1e6e0070) & 0x40; |
| 202 | if (++timeout > TIMEOUT_AST2150) { |
| 203 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 204 | return 0xffffffff; |
| 205 | } |
| 206 | } while (!data); |
| 207 | data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; |
| 208 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 209 | return data; |
| 210 | } |
| 211 | |
| 212 | static int cbrtest_ast2150(struct ast_private *ast) |
| 213 | { |
| 214 | int i; |
| 215 | |
| 216 | for (i = 0; i < 8; i++) |
| 217 | if (mmctestburst2_ast2150(ast, i)) |
| 218 | return 0; |
| 219 | return 1; |
| 220 | } |
| 221 | |
| 222 | static int cbrscan_ast2150(struct ast_private *ast, int busw) |
| 223 | { |
| 224 | u32 patcnt, loop; |
| 225 | |
| 226 | for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) { |
| 227 | ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); |
| 228 | for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) { |
| 229 | if (cbrtest_ast2150(ast)) |
| 230 | break; |
| 231 | } |
| 232 | if (loop == CBR_PASSNUM_AST2150) |
| 233 | return 0; |
| 234 | } |
| 235 | return 1; |
| 236 | } |
| 237 | |
| 238 | |
| 239 | static void cbrdlli_ast2150(struct ast_private *ast, int busw) |
| 240 | { |
| 241 | u32 dll_min[4], dll_max[4], dlli, data, passcnt; |
| 242 | |
| 243 | cbr_start: |
| 244 | dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff; |
| 245 | dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0; |
| 246 | passcnt = 0; |
| 247 | |
| 248 | for (dlli = 0; dlli < 100; dlli++) { |
| 249 | ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); |
| 250 | data = cbrscan_ast2150(ast, busw); |
| 251 | if (data != 0) { |
| 252 | if (data & 0x1) { |
| 253 | if (dll_min[0] > dlli) |
| 254 | dll_min[0] = dlli; |
| 255 | if (dll_max[0] < dlli) |
| 256 | dll_max[0] = dlli; |
| 257 | } |
| 258 | passcnt++; |
| 259 | } else if (passcnt >= CBR_THRESHOLD_AST2150) |
| 260 | goto cbr_start; |
| 261 | } |
| 262 | if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150) |
| 263 | goto cbr_start; |
| 264 | |
| 265 | dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4); |
| 266 | ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); |
| 267 | } |
| 268 | |
| 269 | |
| 270 | |
| 271 | static void ast_init_dram_reg(struct drm_device *dev) |
| 272 | { |
| 273 | struct ast_private *ast = dev->dev_private; |
| 274 | u8 j; |
| 275 | u32 data, temp, i; |
| 276 | uint32_t timeout; |
| 277 | const struct ast_dramstruct *dram_reg_info; |
| 278 | |
| 279 | j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); |
| 280 | |
| 281 | if ((j & 0x80) == 0) { /* VGA only */ |
| 282 | if (ast->chip == AST2000) { |
| 283 | dram_reg_info = ast2000_dram_table_data; |
| 284 | ast_write32(ast, 0xf004, 0x1e6e0000); |
| 285 | ast_write32(ast, 0xf000, 0x1); |
| 286 | ast_write32(ast, 0x10100, 0xa8); |
| 287 | |
| 288 | timeout = 0; |
| 289 | do { |
| 290 | timeout++; |
| 291 | } while ((ast_read32(ast, 0x10100) != 0xa8) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 292 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 293 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 294 | } else {/* AST2100/1100 */ |
| 295 | if (ast->chip == AST2100 || ast->chip == 2200) |
| 296 | dram_reg_info = ast2100_dram_table_data; |
| 297 | else |
| 298 | dram_reg_info = ast1100_dram_table_data; |
| 299 | |
| 300 | ast_write32(ast, 0xf004, 0x1e6e0000); |
| 301 | ast_write32(ast, 0xf000, 0x1); |
| 302 | ast_write32(ast, 0x12000, 0x1688A8A8); |
| 303 | |
| 304 | /* Wait up to 2.5 seconds for device initialization / register unlock */ |
| 305 | for (i = 0; i < 250; i++) { |
| 306 | if (ast_read32(ast, 0x12000) == 0x01) |
| 307 | break; |
| 308 | mdelay(10); |
| 309 | } |
| 310 | if (ast_read32(ast, 0x12000) != 0x01) |
| 311 | dev_err(dev->pdev, "Unable to unlock SCU registers\n"); |
| 312 | |
| 313 | ast_write32(ast, 0x10000, 0xfc600309); |
| 314 | |
| 315 | /* Wait up to 2.5 seconds for device initialization / register unlock */ |
| 316 | for (i = 0; i < 250; i++) { |
| 317 | if (ast_read32(ast, 0x10000) == 0x01) |
| 318 | break; |
| 319 | mdelay(10); |
| 320 | } |
| 321 | if (ast_read32(ast, 0x10000) != 0x01) |
| 322 | dev_err(dev->pdev, "Unable to unlock SDRAM control registers\n"); |
| 323 | } |
| 324 | |
| 325 | while (dram_reg_info->index != 0xffff) { |
| 326 | if (dram_reg_info->index == 0xff00) {/* delay fn */ |
| 327 | for (i = 0; i < 15; i++) |
| 328 | udelay(dram_reg_info->data); |
| 329 | } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) { |
| 330 | data = dram_reg_info->data; |
| 331 | if (ast->dram_type == AST_DRAM_1Gx16) |
| 332 | data = 0x00000d89; |
| 333 | else if (ast->dram_type == AST_DRAM_1Gx32) |
| 334 | data = 0x00000c8d; |
| 335 | |
| 336 | temp = ast_read32(ast, 0x12070); |
| 337 | temp &= 0xc; |
| 338 | temp <<= 2; |
| 339 | ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); |
| 340 | } else |
| 341 | ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data); |
| 342 | dram_reg_info++; |
| 343 | } |
| 344 | |
| 345 | /* AST 2100/2150 DRAM calibration */ |
| 346 | data = ast_read32(ast, 0x10120); |
| 347 | if (data == 0x5061) { /* 266Mhz */ |
| 348 | data = ast_read32(ast, 0x10004); |
| 349 | if (data & 0x40) |
| 350 | cbrdlli_ast2150(ast, 16); /* 16 bits */ |
| 351 | else |
| 352 | cbrdlli_ast2150(ast, 32); /* 32 bits */ |
| 353 | } |
| 354 | |
| 355 | switch (ast->chip) { |
| 356 | case AST2000: |
| 357 | temp = ast_read32(ast, 0x10140); |
| 358 | ast_write32(ast, 0x10140, temp | 0x40); |
| 359 | break; |
| 360 | case AST1100: |
| 361 | case AST2100: |
| 362 | case AST2200: |
| 363 | case AST2150: |
| 364 | temp = ast_read32(ast, 0x1200c); |
| 365 | ast_write32(ast, 0x1200c, temp & 0xfffffffd); |
| 366 | temp = ast_read32(ast, 0x12040); |
| 367 | ast_write32(ast, 0x12040, temp | 0x40); |
| 368 | break; |
| 369 | default: |
| 370 | break; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | /* wait ready */ |
| 375 | /* Wait up to 2.5 seconds for device to become ready */ |
| 376 | for (i = 0; i < 250; i++) { |
| 377 | j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); |
| 378 | mdelay(10); |
| 379 | if ((j & 0x40) != 0) |
| 380 | break; |
| 381 | } |
| 382 | if ((j & 0x40) == 0) |
| 383 | dev_err(dev->pdev, "Timeout while waiting for device to signal ready\n"); |
| 384 | } |
| 385 | |
| 386 | void ast_post_gpu(struct drm_device *dev) |
| 387 | { |
| 388 | u32 reg; |
| 389 | struct ast_private *ast = dev->dev_private; |
| 390 | |
| 391 | pci_read_config_dword(ast->dev->pdev, 0x04, ®); |
| 392 | reg |= 0x3; |
| 393 | pci_write_config_dword(ast->dev->pdev, 0x04, reg); |
| 394 | |
| 395 | ast_enable_vga(dev); |
| 396 | ast_enable_mmio(dev); |
| 397 | ast_open_key(ast); |
| 398 | ast_set_def_ext_reg(dev); |
| 399 | |
| 400 | if (ast->chip == AST2300 || ast->chip == AST2400) |
| 401 | ast_init_dram_2300(dev); |
| 402 | else |
| 403 | ast_init_dram_reg(dev); |
| 404 | |
| 405 | ast_init_3rdtx(dev); |
| 406 | } |
| 407 | |
| 408 | /* AST 2300 DRAM settings */ |
| 409 | #define AST_DDR3 0 |
| 410 | #define AST_DDR2 1 |
| 411 | |
| 412 | struct ast2300_dram_param { |
| 413 | u32 dram_type; |
| 414 | u32 dram_chipid; |
| 415 | u32 dram_freq; |
| 416 | u32 vram_size; |
| 417 | u32 odt; |
| 418 | u32 wodt; |
| 419 | u32 rodt; |
| 420 | u32 dram_config; |
| 421 | u32 reg_PERIOD; |
| 422 | u32 reg_MADJ; |
| 423 | u32 reg_SADJ; |
| 424 | u32 reg_MRS; |
| 425 | u32 reg_EMRS; |
| 426 | u32 reg_AC1; |
| 427 | u32 reg_AC2; |
| 428 | u32 reg_DQSIC; |
| 429 | u32 reg_DRV; |
| 430 | u32 reg_IOZ; |
| 431 | u32 reg_DQIDLY; |
| 432 | u32 reg_FREQ; |
| 433 | u32 madj_max; |
| 434 | u32 dll2_finetune_step; |
| 435 | }; |
| 436 | |
| 437 | /* |
| 438 | * DQSI DLL CBR Setting |
| 439 | */ |
| 440 | #define CBR_SIZE0 ((1 << 10) - 1) |
| 441 | #define CBR_SIZE1 ((4 << 10) - 1) |
| 442 | #define CBR_SIZE2 ((64 << 10) - 1) |
| 443 | #define CBR_PASSNUM 5 |
| 444 | #define CBR_PASSNUM2 5 |
| 445 | #define CBR_THRESHOLD 10 |
| 446 | #define CBR_THRESHOLD2 10 |
| 447 | #define TIMEOUT 5000000 |
| 448 | #define CBR_PATNUM 8 |
| 449 | |
| 450 | static const u32 pattern[8] = { |
| 451 | 0xFF00FF00, |
| 452 | 0xCC33CC33, |
| 453 | 0xAA55AA55, |
| 454 | 0x88778877, |
| 455 | 0x92CC4D6E, |
| 456 | 0x543D3CDE, |
| 457 | 0xF1E843C7, |
| 458 | 0x7C61D253 |
| 459 | }; |
| 460 | |
| 461 | static int mmc_test_burst(struct ast_private *ast, u32 datagen) |
| 462 | { |
| 463 | u32 data, timeout; |
| 464 | |
| 465 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 466 | ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3)); |
| 467 | timeout = 0; |
| 468 | do { |
| 469 | data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; |
| 470 | if (data & 0x2000) { |
| 471 | return 0; |
| 472 | } |
| 473 | if (++timeout > TIMEOUT) { |
| 474 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 475 | return 0; |
| 476 | } |
| 477 | } while (!data); |
| 478 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 479 | return 1; |
| 480 | } |
| 481 | |
| 482 | static int mmc_test_burst2(struct ast_private *ast, u32 datagen) |
| 483 | { |
| 484 | u32 data, timeout; |
| 485 | |
| 486 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 487 | ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3)); |
| 488 | timeout = 0; |
| 489 | do { |
| 490 | data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; |
| 491 | if (++timeout > TIMEOUT) { |
| 492 | ast_moutdwm(ast, 0x1e6e0070, 0x0); |
| 493 | return -1; |
| 494 | } |
| 495 | } while (!data); |
| 496 | data = ast_mindwm(ast, 0x1e6e0078); |
| 497 | data = (data | (data >> 16)) & 0xffff; |
| 498 | ast_moutdwm(ast, 0x1e6e0070, 0x0); |
| 499 | return data; |
| 500 | } |
| 501 | |
| 502 | static int mmc_test_single(struct ast_private *ast, u32 datagen) |
| 503 | { |
| 504 | u32 data, timeout; |
| 505 | |
| 506 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 507 | ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3)); |
| 508 | timeout = 0; |
| 509 | do { |
| 510 | data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; |
| 511 | if (data & 0x2000) |
| 512 | return 0; |
| 513 | if (++timeout > TIMEOUT) { |
| 514 | ast_moutdwm(ast, 0x1e6e0070, 0x0); |
| 515 | return 0; |
| 516 | } |
| 517 | } while (!data); |
| 518 | ast_moutdwm(ast, 0x1e6e0070, 0x0); |
| 519 | return 1; |
| 520 | } |
| 521 | |
| 522 | static int mmc_test_single2(struct ast_private *ast, u32 datagen) |
| 523 | { |
| 524 | u32 data, timeout; |
| 525 | |
| 526 | ast_moutdwm(ast, 0x1e6e0070, 0x00000000); |
| 527 | ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); |
| 528 | timeout = 0; |
| 529 | do { |
| 530 | data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; |
| 531 | if (++timeout > TIMEOUT) { |
| 532 | ast_moutdwm(ast, 0x1e6e0070, 0x0); |
| 533 | return -1; |
| 534 | } |
| 535 | } while (!data); |
| 536 | data = ast_mindwm(ast, 0x1e6e0078); |
| 537 | data = (data | (data >> 16)) & 0xffff; |
| 538 | ast_moutdwm(ast, 0x1e6e0070, 0x0); |
| 539 | return data; |
| 540 | } |
| 541 | |
| 542 | static int cbr_test(struct ast_private *ast) |
| 543 | { |
| 544 | u32 data; |
| 545 | int i; |
| 546 | data = mmc_test_single2(ast, 0); |
| 547 | if ((data & 0xff) && (data & 0xff00)) |
| 548 | return 0; |
| 549 | for (i = 0; i < 8; i++) { |
| 550 | data = mmc_test_burst2(ast, i); |
| 551 | if ((data & 0xff) && (data & 0xff00)) |
| 552 | return 0; |
| 553 | } |
| 554 | if (!data) |
| 555 | return 3; |
| 556 | else if (data & 0xff) |
| 557 | return 2; |
| 558 | return 1; |
| 559 | } |
| 560 | |
| 561 | static int cbr_scan(struct ast_private *ast) |
| 562 | { |
| 563 | u32 data, data2, patcnt, loop; |
| 564 | |
| 565 | data2 = 3; |
| 566 | for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { |
| 567 | ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); |
| 568 | for (loop = 0; loop < CBR_PASSNUM2; loop++) { |
| 569 | if ((data = cbr_test(ast)) != 0) { |
| 570 | data2 &= data; |
| 571 | if (!data2) |
| 572 | return 0; |
| 573 | break; |
| 574 | } |
| 575 | } |
| 576 | if (loop == CBR_PASSNUM2) |
| 577 | return 0; |
| 578 | } |
| 579 | return data2; |
| 580 | } |
| 581 | |
| 582 | static u32 cbr_test2(struct ast_private *ast) |
| 583 | { |
| 584 | u32 data; |
| 585 | |
| 586 | data = mmc_test_burst2(ast, 0); |
| 587 | if (data == 0xffff) |
| 588 | return 0; |
| 589 | data |= mmc_test_single2(ast, 0); |
| 590 | if (data == 0xffff) |
| 591 | return 0; |
| 592 | |
| 593 | return ~data & 0xffff; |
| 594 | } |
| 595 | |
| 596 | static u32 cbr_scan2(struct ast_private *ast) |
| 597 | { |
| 598 | u32 data, data2, patcnt, loop; |
| 599 | |
| 600 | data2 = 0xffff; |
| 601 | for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { |
| 602 | ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); |
| 603 | for (loop = 0; loop < CBR_PASSNUM2; loop++) { |
| 604 | if ((data = cbr_test2(ast)) != 0) { |
| 605 | data2 &= data; |
| 606 | if (!data2) |
| 607 | return 0; |
| 608 | break; |
| 609 | } |
| 610 | } |
| 611 | if (loop == CBR_PASSNUM2) |
| 612 | return 0; |
| 613 | } |
| 614 | return data2; |
| 615 | } |
| 616 | |
| 617 | static u32 cbr_test3(struct ast_private *ast) |
| 618 | { |
| 619 | if (!mmc_test_burst(ast, 0)) |
| 620 | return 0; |
| 621 | if (!mmc_test_single(ast, 0)) |
| 622 | return 0; |
| 623 | return 1; |
| 624 | } |
| 625 | |
| 626 | static u32 cbr_scan3(struct ast_private *ast) |
| 627 | { |
| 628 | u32 patcnt, loop; |
| 629 | |
| 630 | for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { |
| 631 | ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); |
| 632 | for (loop = 0; loop < 2; loop++) { |
| 633 | if (cbr_test3(ast)) |
| 634 | break; |
| 635 | } |
| 636 | if (loop == 2) |
| 637 | return 0; |
| 638 | } |
| 639 | return 1; |
| 640 | } |
| 641 | |
| 642 | static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) |
| 643 | { |
| 644 | u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0; |
| 645 | bool status = false; |
| 646 | FINETUNE_START: |
| 647 | for (cnt = 0; cnt < 16; cnt++) { |
| 648 | dllmin[cnt] = 0xff; |
| 649 | dllmax[cnt] = 0x0; |
| 650 | } |
| 651 | passcnt = 0; |
| 652 | for (dlli = 0; dlli < 76; dlli++) { |
| 653 | ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); |
| 654 | ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); |
| 655 | data = cbr_scan2(ast); |
| 656 | if (data != 0) { |
| 657 | mask = 0x00010001; |
| 658 | for (cnt = 0; cnt < 16; cnt++) { |
| 659 | if (data & mask) { |
| 660 | if (dllmin[cnt] > dlli) { |
| 661 | dllmin[cnt] = dlli; |
| 662 | } |
| 663 | if (dllmax[cnt] < dlli) { |
| 664 | dllmax[cnt] = dlli; |
| 665 | } |
| 666 | } |
| 667 | mask <<= 1; |
| 668 | } |
| 669 | passcnt++; |
| 670 | } else if (passcnt >= CBR_THRESHOLD2) { |
| 671 | break; |
| 672 | } |
| 673 | } |
| 674 | gold_sadj[0] = 0x0; |
| 675 | passcnt = 0; |
| 676 | for (cnt = 0; cnt < 16; cnt++) { |
| 677 | if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { |
| 678 | gold_sadj[0] += dllmin[cnt]; |
| 679 | passcnt++; |
| 680 | } |
| 681 | } |
| 682 | if (retry++ > 10) |
| 683 | goto FINETUNE_DONE; |
| 684 | if (passcnt != 16) { |
| 685 | goto FINETUNE_START; |
| 686 | } |
| 687 | status = true; |
| 688 | FINETUNE_DONE: |
| 689 | gold_sadj[0] = gold_sadj[0] >> 4; |
| 690 | gold_sadj[1] = gold_sadj[0]; |
| 691 | |
| 692 | data = 0; |
| 693 | for (cnt = 0; cnt < 8; cnt++) { |
| 694 | data >>= 3; |
| 695 | if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { |
| 696 | dlli = dllmin[cnt]; |
| 697 | if (gold_sadj[0] >= dlli) { |
| 698 | dlli = ((gold_sadj[0] - dlli) * 19) >> 5; |
| 699 | if (dlli > 3) { |
| 700 | dlli = 3; |
| 701 | } |
| 702 | } else { |
| 703 | dlli = ((dlli - gold_sadj[0]) * 19) >> 5; |
| 704 | if (dlli > 4) { |
| 705 | dlli = 4; |
| 706 | } |
| 707 | dlli = (8 - dlli) & 0x7; |
| 708 | } |
| 709 | data |= dlli << 21; |
| 710 | } |
| 711 | } |
| 712 | ast_moutdwm(ast, 0x1E6E0080, data); |
| 713 | |
| 714 | data = 0; |
| 715 | for (cnt = 8; cnt < 16; cnt++) { |
| 716 | data >>= 3; |
| 717 | if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { |
| 718 | dlli = dllmin[cnt]; |
| 719 | if (gold_sadj[1] >= dlli) { |
| 720 | dlli = ((gold_sadj[1] - dlli) * 19) >> 5; |
| 721 | if (dlli > 3) { |
| 722 | dlli = 3; |
| 723 | } else { |
| 724 | dlli = (dlli - 1) & 0x7; |
| 725 | } |
| 726 | } else { |
| 727 | dlli = ((dlli - gold_sadj[1]) * 19) >> 5; |
| 728 | dlli += 1; |
| 729 | if (dlli > 4) { |
| 730 | dlli = 4; |
| 731 | } |
| 732 | dlli = (8 - dlli) & 0x7; |
| 733 | } |
| 734 | data |= dlli << 21; |
| 735 | } |
| 736 | } |
| 737 | ast_moutdwm(ast, 0x1E6E0084, data); |
| 738 | return status; |
| 739 | } /* finetuneDQI_L */ |
| 740 | |
| 741 | static void finetuneDQSI(struct ast_private *ast) |
| 742 | { |
| 743 | u32 dlli, dqsip, dqidly; |
| 744 | u32 reg_mcr18, reg_mcr0c, passcnt[2], diff; |
| 745 | u32 g_dqidly, g_dqsip, g_margin, g_side; |
| 746 | u16 pass[32][2][2]; |
| 747 | char tag[2][76]; |
| 748 | |
| 749 | /* Disable DQI CBR */ |
| 750 | reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); |
| 751 | reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); |
| 752 | reg_mcr18 &= 0x0000ffff; |
| 753 | ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); |
| 754 | |
| 755 | for (dlli = 0; dlli < 76; dlli++) { |
| 756 | tag[0][dlli] = 0x0; |
| 757 | tag[1][dlli] = 0x0; |
| 758 | } |
| 759 | for (dqidly = 0; dqidly < 32; dqidly++) { |
| 760 | pass[dqidly][0][0] = 0xff; |
| 761 | pass[dqidly][0][1] = 0x0; |
| 762 | pass[dqidly][1][0] = 0xff; |
| 763 | pass[dqidly][1][1] = 0x0; |
| 764 | } |
| 765 | for (dqidly = 0; dqidly < 32; dqidly++) { |
| 766 | passcnt[0] = passcnt[1] = 0; |
| 767 | for (dqsip = 0; dqsip < 2; dqsip++) { |
| 768 | ast_moutdwm(ast, 0x1E6E000C, 0); |
| 769 | ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); |
| 770 | ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); |
| 771 | for (dlli = 0; dlli < 76; dlli++) { |
| 772 | ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); |
| 773 | ast_moutdwm(ast, 0x1E6E0070, 0); |
| 774 | ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); |
| 775 | if (cbr_scan3(ast)) { |
| 776 | if (dlli == 0) |
| 777 | break; |
| 778 | passcnt[dqsip]++; |
| 779 | tag[dqsip][dlli] = 'P'; |
| 780 | if (dlli < pass[dqidly][dqsip][0]) |
| 781 | pass[dqidly][dqsip][0] = (u16) dlli; |
| 782 | if (dlli > pass[dqidly][dqsip][1]) |
| 783 | pass[dqidly][dqsip][1] = (u16) dlli; |
| 784 | } else if (passcnt[dqsip] >= 5) |
| 785 | break; |
| 786 | else { |
| 787 | pass[dqidly][dqsip][0] = 0xff; |
| 788 | pass[dqidly][dqsip][1] = 0x0; |
| 789 | } |
| 790 | } |
| 791 | } |
| 792 | if (passcnt[0] == 0 && passcnt[1] == 0) |
| 793 | dqidly++; |
| 794 | } |
| 795 | /* Search margin */ |
| 796 | g_dqidly = g_dqsip = g_margin = g_side = 0; |
| 797 | |
| 798 | for (dqidly = 0; dqidly < 32; dqidly++) { |
| 799 | for (dqsip = 0; dqsip < 2; dqsip++) { |
| 800 | if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1]) |
| 801 | continue; |
| 802 | diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0]; |
| 803 | if ((diff+2) < g_margin) |
| 804 | continue; |
| 805 | passcnt[0] = passcnt[1] = 0; |
| 806 | for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++); |
| 807 | for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++); |
| 808 | if (passcnt[0] > passcnt[1]) |
| 809 | passcnt[0] = passcnt[1]; |
| 810 | passcnt[1] = 0; |
| 811 | if (passcnt[0] > g_side) |
| 812 | passcnt[1] = passcnt[0] - g_side; |
| 813 | if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) { |
| 814 | g_margin = diff; |
| 815 | g_dqidly = dqidly; |
| 816 | g_dqsip = dqsip; |
| 817 | g_side = passcnt[0]; |
| 818 | } else if (passcnt[1] > 1 && g_side < 8) { |
| 819 | if (diff > g_margin) |
| 820 | g_margin = diff; |
| 821 | g_dqidly = dqidly; |
| 822 | g_dqsip = dqsip; |
| 823 | g_side = passcnt[0]; |
| 824 | } |
| 825 | } |
| 826 | } |
| 827 | reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23); |
| 828 | ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); |
| 829 | |
| 830 | } |
| 831 | static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param) |
| 832 | { |
| 833 | u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0; |
| 834 | bool status = false; |
| 835 | |
| 836 | finetuneDQSI(ast); |
| 837 | if (finetuneDQI_L(ast, param) == false) |
| 838 | return status; |
| 839 | |
| 840 | CBR_START2: |
| 841 | dllmin[0] = dllmin[1] = 0xff; |
| 842 | dllmax[0] = dllmax[1] = 0x0; |
| 843 | passcnt = 0; |
| 844 | for (dlli = 0; dlli < 76; dlli++) { |
| 845 | ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); |
| 846 | ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); |
| 847 | data = cbr_scan(ast); |
| 848 | if (data != 0) { |
| 849 | if (data & 0x1) { |
| 850 | if (dllmin[0] > dlli) { |
| 851 | dllmin[0] = dlli; |
| 852 | } |
| 853 | if (dllmax[0] < dlli) { |
| 854 | dllmax[0] = dlli; |
| 855 | } |
| 856 | } |
| 857 | if (data & 0x2) { |
| 858 | if (dllmin[1] > dlli) { |
| 859 | dllmin[1] = dlli; |
| 860 | } |
| 861 | if (dllmax[1] < dlli) { |
| 862 | dllmax[1] = dlli; |
| 863 | } |
| 864 | } |
| 865 | passcnt++; |
| 866 | } else if (passcnt >= CBR_THRESHOLD) { |
| 867 | break; |
| 868 | } |
| 869 | } |
| 870 | if (retry++ > 10) |
| 871 | goto CBR_DONE2; |
| 872 | if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) { |
| 873 | goto CBR_START2; |
| 874 | } |
| 875 | if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) { |
| 876 | goto CBR_START2; |
| 877 | } |
| 878 | status = true; |
| 879 | CBR_DONE2: |
| 880 | dlli = (dllmin[1] + dllmax[1]) >> 1; |
| 881 | dlli <<= 8; |
| 882 | dlli += (dllmin[0] + dllmax[0]) >> 1; |
| 883 | ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); |
| 884 | return status; |
| 885 | } /* CBRDLL2 */ |
| 886 | |
| 887 | static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param) |
| 888 | { |
| 889 | u32 trap, trap_AC2, trap_MRS; |
| 890 | |
| 891 | ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); |
| 892 | |
| 893 | /* Ger trap info */ |
| 894 | trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; |
| 895 | trap_AC2 = 0x00020000 + (trap << 16); |
| 896 | trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19); |
| 897 | trap_MRS = 0x00000010 + (trap << 4); |
| 898 | trap_MRS |= ((trap & 0x2) << 18); |
| 899 | |
| 900 | param->reg_MADJ = 0x00034C4C; |
| 901 | param->reg_SADJ = 0x00001800; |
| 902 | param->reg_DRV = 0x000000F0; |
| 903 | param->reg_PERIOD = param->dram_freq; |
| 904 | param->rodt = 0; |
| 905 | |
| 906 | switch (param->dram_freq) { |
| 907 | case 336: |
| 908 | ast_moutdwm(ast, 0x1E6E2020, 0x0190); |
| 909 | param->wodt = 0; |
| 910 | param->reg_AC1 = 0x22202725; |
| 911 | param->reg_AC2 = 0xAA007613 | trap_AC2; |
| 912 | param->reg_DQSIC = 0x000000BA; |
| 913 | param->reg_MRS = 0x04001400 | trap_MRS; |
| 914 | param->reg_EMRS = 0x00000000; |
| 915 | param->reg_IOZ = 0x00000023; |
| 916 | param->reg_DQIDLY = 0x00000074; |
| 917 | param->reg_FREQ = 0x00004DC0; |
| 918 | param->madj_max = 96; |
| 919 | param->dll2_finetune_step = 3; |
| 920 | switch (param->dram_chipid) { |
| 921 | default: |
| 922 | case AST_DRAM_512Mx16: |
| 923 | case AST_DRAM_1Gx16: |
| 924 | param->reg_AC2 = 0xAA007613 | trap_AC2; |
| 925 | break; |
| 926 | case AST_DRAM_2Gx16: |
| 927 | param->reg_AC2 = 0xAA00761C | trap_AC2; |
| 928 | break; |
| 929 | case AST_DRAM_4Gx16: |
| 930 | param->reg_AC2 = 0xAA007636 | trap_AC2; |
| 931 | break; |
| 932 | } |
| 933 | break; |
| 934 | default: |
| 935 | case 396: |
| 936 | ast_moutdwm(ast, 0x1E6E2020, 0x03F1); |
| 937 | param->wodt = 1; |
| 938 | param->reg_AC1 = 0x33302825; |
| 939 | param->reg_AC2 = 0xCC009617 | trap_AC2; |
| 940 | param->reg_DQSIC = 0x000000E2; |
| 941 | param->reg_MRS = 0x04001600 | trap_MRS; |
| 942 | param->reg_EMRS = 0x00000000; |
| 943 | param->reg_IOZ = 0x00000034; |
| 944 | param->reg_DRV = 0x000000FA; |
| 945 | param->reg_DQIDLY = 0x00000089; |
| 946 | param->reg_FREQ = 0x00005040; |
| 947 | param->madj_max = 96; |
| 948 | param->dll2_finetune_step = 4; |
| 949 | |
| 950 | switch (param->dram_chipid) { |
| 951 | default: |
| 952 | case AST_DRAM_512Mx16: |
| 953 | case AST_DRAM_1Gx16: |
| 954 | param->reg_AC2 = 0xCC009617 | trap_AC2; |
| 955 | break; |
| 956 | case AST_DRAM_2Gx16: |
| 957 | param->reg_AC2 = 0xCC009622 | trap_AC2; |
| 958 | break; |
| 959 | case AST_DRAM_4Gx16: |
| 960 | param->reg_AC2 = 0xCC00963F | trap_AC2; |
| 961 | break; |
| 962 | } |
| 963 | break; |
| 964 | |
| 965 | case 408: |
| 966 | ast_moutdwm(ast, 0x1E6E2020, 0x01F0); |
| 967 | param->wodt = 1; |
| 968 | param->reg_AC1 = 0x33302825; |
| 969 | param->reg_AC2 = 0xCC009617 | trap_AC2; |
| 970 | param->reg_DQSIC = 0x000000E2; |
| 971 | param->reg_MRS = 0x04001600 | trap_MRS; |
| 972 | param->reg_EMRS = 0x00000000; |
| 973 | param->reg_IOZ = 0x00000023; |
| 974 | param->reg_DRV = 0x000000FA; |
| 975 | param->reg_DQIDLY = 0x00000089; |
| 976 | param->reg_FREQ = 0x000050C0; |
| 977 | param->madj_max = 96; |
| 978 | param->dll2_finetune_step = 4; |
| 979 | |
| 980 | switch (param->dram_chipid) { |
| 981 | default: |
| 982 | case AST_DRAM_512Mx16: |
| 983 | case AST_DRAM_1Gx16: |
| 984 | param->reg_AC2 = 0xCC009617 | trap_AC2; |
| 985 | break; |
| 986 | case AST_DRAM_2Gx16: |
| 987 | param->reg_AC2 = 0xCC009622 | trap_AC2; |
| 988 | break; |
| 989 | case AST_DRAM_4Gx16: |
| 990 | param->reg_AC2 = 0xCC00963F | trap_AC2; |
| 991 | break; |
| 992 | } |
| 993 | |
| 994 | break; |
| 995 | case 456: |
| 996 | ast_moutdwm(ast, 0x1E6E2020, 0x0230); |
| 997 | param->wodt = 0; |
| 998 | param->reg_AC1 = 0x33302926; |
| 999 | param->reg_AC2 = 0xCD44961A; |
| 1000 | param->reg_DQSIC = 0x000000FC; |
| 1001 | param->reg_MRS = 0x00081830; |
| 1002 | param->reg_EMRS = 0x00000000; |
| 1003 | param->reg_IOZ = 0x00000045; |
| 1004 | param->reg_DQIDLY = 0x00000097; |
| 1005 | param->reg_FREQ = 0x000052C0; |
| 1006 | param->madj_max = 88; |
| 1007 | param->dll2_finetune_step = 4; |
| 1008 | break; |
| 1009 | case 504: |
| 1010 | ast_moutdwm(ast, 0x1E6E2020, 0x0270); |
| 1011 | param->wodt = 1; |
| 1012 | param->reg_AC1 = 0x33302926; |
| 1013 | param->reg_AC2 = 0xDE44A61D; |
| 1014 | param->reg_DQSIC = 0x00000117; |
| 1015 | param->reg_MRS = 0x00081A30; |
| 1016 | param->reg_EMRS = 0x00000000; |
| 1017 | param->reg_IOZ = 0x070000BB; |
| 1018 | param->reg_DQIDLY = 0x000000A0; |
| 1019 | param->reg_FREQ = 0x000054C0; |
| 1020 | param->madj_max = 79; |
| 1021 | param->dll2_finetune_step = 4; |
| 1022 | break; |
| 1023 | case 528: |
| 1024 | ast_moutdwm(ast, 0x1E6E2020, 0x0290); |
| 1025 | param->wodt = 1; |
| 1026 | param->rodt = 1; |
| 1027 | param->reg_AC1 = 0x33302926; |
| 1028 | param->reg_AC2 = 0xEF44B61E; |
| 1029 | param->reg_DQSIC = 0x00000125; |
| 1030 | param->reg_MRS = 0x00081A30; |
| 1031 | param->reg_EMRS = 0x00000040; |
| 1032 | param->reg_DRV = 0x000000F5; |
| 1033 | param->reg_IOZ = 0x00000023; |
| 1034 | param->reg_DQIDLY = 0x00000088; |
| 1035 | param->reg_FREQ = 0x000055C0; |
| 1036 | param->madj_max = 76; |
| 1037 | param->dll2_finetune_step = 3; |
| 1038 | break; |
| 1039 | case 576: |
| 1040 | ast_moutdwm(ast, 0x1E6E2020, 0x0140); |
| 1041 | param->reg_MADJ = 0x00136868; |
| 1042 | param->reg_SADJ = 0x00004534; |
| 1043 | param->wodt = 1; |
| 1044 | param->rodt = 1; |
| 1045 | param->reg_AC1 = 0x33302A37; |
| 1046 | param->reg_AC2 = 0xEF56B61E; |
| 1047 | param->reg_DQSIC = 0x0000013F; |
| 1048 | param->reg_MRS = 0x00101A50; |
| 1049 | param->reg_EMRS = 0x00000040; |
| 1050 | param->reg_DRV = 0x000000FA; |
| 1051 | param->reg_IOZ = 0x00000023; |
| 1052 | param->reg_DQIDLY = 0x00000078; |
| 1053 | param->reg_FREQ = 0x000057C0; |
| 1054 | param->madj_max = 136; |
| 1055 | param->dll2_finetune_step = 3; |
| 1056 | break; |
| 1057 | case 600: |
| 1058 | ast_moutdwm(ast, 0x1E6E2020, 0x02E1); |
| 1059 | param->reg_MADJ = 0x00136868; |
| 1060 | param->reg_SADJ = 0x00004534; |
| 1061 | param->wodt = 1; |
| 1062 | param->rodt = 1; |
| 1063 | param->reg_AC1 = 0x32302A37; |
| 1064 | param->reg_AC2 = 0xDF56B61F; |
| 1065 | param->reg_DQSIC = 0x0000014D; |
| 1066 | param->reg_MRS = 0x00101A50; |
| 1067 | param->reg_EMRS = 0x00000004; |
| 1068 | param->reg_DRV = 0x000000F5; |
| 1069 | param->reg_IOZ = 0x00000023; |
| 1070 | param->reg_DQIDLY = 0x00000078; |
| 1071 | param->reg_FREQ = 0x000058C0; |
| 1072 | param->madj_max = 132; |
| 1073 | param->dll2_finetune_step = 3; |
| 1074 | break; |
| 1075 | case 624: |
| 1076 | ast_moutdwm(ast, 0x1E6E2020, 0x0160); |
| 1077 | param->reg_MADJ = 0x00136868; |
| 1078 | param->reg_SADJ = 0x00004534; |
| 1079 | param->wodt = 1; |
| 1080 | param->rodt = 1; |
| 1081 | param->reg_AC1 = 0x32302A37; |
| 1082 | param->reg_AC2 = 0xEF56B621; |
| 1083 | param->reg_DQSIC = 0x0000015A; |
| 1084 | param->reg_MRS = 0x02101A50; |
| 1085 | param->reg_EMRS = 0x00000004; |
| 1086 | param->reg_DRV = 0x000000F5; |
| 1087 | param->reg_IOZ = 0x00000034; |
| 1088 | param->reg_DQIDLY = 0x00000078; |
| 1089 | param->reg_FREQ = 0x000059C0; |
| 1090 | param->madj_max = 128; |
| 1091 | param->dll2_finetune_step = 3; |
| 1092 | break; |
| 1093 | } /* switch freq */ |
| 1094 | |
| 1095 | switch (param->dram_chipid) { |
| 1096 | case AST_DRAM_512Mx16: |
| 1097 | param->dram_config = 0x130; |
| 1098 | break; |
| 1099 | default: |
| 1100 | case AST_DRAM_1Gx16: |
| 1101 | param->dram_config = 0x131; |
| 1102 | break; |
| 1103 | case AST_DRAM_2Gx16: |
| 1104 | param->dram_config = 0x132; |
| 1105 | break; |
| 1106 | case AST_DRAM_4Gx16: |
| 1107 | param->dram_config = 0x133; |
| 1108 | break; |
| 1109 | } /* switch size */ |
| 1110 | |
| 1111 | switch (param->vram_size) { |
| 1112 | default: |
| 1113 | case AST_VIDMEM_SIZE_8M: |
| 1114 | param->dram_config |= 0x00; |
| 1115 | break; |
| 1116 | case AST_VIDMEM_SIZE_16M: |
| 1117 | param->dram_config |= 0x04; |
| 1118 | break; |
| 1119 | case AST_VIDMEM_SIZE_32M: |
| 1120 | param->dram_config |= 0x08; |
| 1121 | break; |
| 1122 | case AST_VIDMEM_SIZE_64M: |
| 1123 | param->dram_config |= 0x0c; |
| 1124 | break; |
| 1125 | } |
| 1126 | |
| 1127 | } |
| 1128 | |
| 1129 | static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param) |
| 1130 | { |
| 1131 | u32 data, data2, retry = 0; |
| 1132 | uint32_t timeout; |
| 1133 | uint32_t timeout2; |
| 1134 | |
| 1135 | ddr3_init_start: |
| 1136 | ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); |
| 1137 | ast_moutdwm(ast, 0x1E6E0018, 0x00000100); |
| 1138 | ast_moutdwm(ast, 0x1E6E0024, 0x00000000); |
| 1139 | ast_moutdwm(ast, 0x1E6E0034, 0x00000000); |
| 1140 | udelay(10); |
| 1141 | ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); |
| 1142 | ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); |
| 1143 | udelay(10); |
| 1144 | ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); |
| 1145 | udelay(10); |
| 1146 | |
| 1147 | ast_moutdwm(ast, 0x1E6E0004, param->dram_config); |
| 1148 | ast_moutdwm(ast, 0x1E6E0008, 0x90040f); |
| 1149 | ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); |
| 1150 | ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); |
| 1151 | ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); |
| 1152 | ast_moutdwm(ast, 0x1E6E0080, 0x00000000); |
| 1153 | ast_moutdwm(ast, 0x1E6E0084, 0x00000000); |
| 1154 | ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); |
| 1155 | ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); |
| 1156 | ast_moutdwm(ast, 0x1E6E0018, 0x00002370); |
| 1157 | ast_moutdwm(ast, 0x1E6E0038, 0x00000000); |
| 1158 | ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); |
| 1159 | ast_moutdwm(ast, 0x1E6E0044, 0x22222222); |
| 1160 | ast_moutdwm(ast, 0x1E6E0048, 0x22222222); |
| 1161 | ast_moutdwm(ast, 0x1E6E004C, 0x00000002); |
| 1162 | ast_moutdwm(ast, 0x1E6E0050, 0x80000000); |
| 1163 | ast_moutdwm(ast, 0x1E6E0050, 0x00000000); |
| 1164 | ast_moutdwm(ast, 0x1E6E0054, 0); |
| 1165 | ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); |
| 1166 | ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); |
| 1167 | ast_moutdwm(ast, 0x1E6E0070, 0x00000000); |
| 1168 | ast_moutdwm(ast, 0x1E6E0074, 0x00000000); |
| 1169 | ast_moutdwm(ast, 0x1E6E0078, 0x00000000); |
| 1170 | ast_moutdwm(ast, 0x1E6E007C, 0x00000000); |
| 1171 | /* Wait MCLK2X lock to MCLK */ |
| 1172 | timeout = 0; |
| 1173 | do { |
| 1174 | data = ast_mindwm(ast, 0x1E6E001C); |
| 1175 | timeout++; |
| 1176 | } while ((!(data & 0x08000000)) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1177 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1178 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1179 | data = ast_mindwm(ast, 0x1E6E001C); |
| 1180 | data = (data >> 8) & 0xff; |
| 1181 | timeout = 0; |
| 1182 | while (((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)) { |
| 1183 | data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; |
| 1184 | if ((data2 & 0xff) > param->madj_max) { |
| 1185 | break; |
| 1186 | } |
| 1187 | ast_moutdwm(ast, 0x1E6E0064, data2); |
| 1188 | if (data2 & 0x00100000) { |
| 1189 | data2 = ((data2 & 0xff) >> 3) + 3; |
| 1190 | } else { |
| 1191 | data2 = ((data2 & 0xff) >> 2) + 5; |
| 1192 | } |
| 1193 | data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; |
| 1194 | data2 += data & 0xff; |
| 1195 | data = data | (data2 << 8); |
| 1196 | ast_moutdwm(ast, 0x1E6E0068, data); |
| 1197 | udelay(10); |
| 1198 | ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); |
| 1199 | udelay(10); |
| 1200 | data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; |
| 1201 | ast_moutdwm(ast, 0x1E6E0018, data); |
| 1202 | data = data | 0x200; |
| 1203 | ast_moutdwm(ast, 0x1E6E0018, data); |
| 1204 | timeout2 = 0; |
| 1205 | do { |
| 1206 | data = ast_mindwm(ast, 0x1E6E001C); |
| 1207 | timeout2++; |
| 1208 | } while ((!(data & 0x08000000)) && (timeout2 < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1209 | if (timeout2 >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1210 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1211 | |
| 1212 | data = ast_mindwm(ast, 0x1E6E001C); |
| 1213 | data = (data >> 8) & 0xff; |
| 1214 | |
| 1215 | timeout++; |
| 1216 | } |
| 1217 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1218 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1219 | ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); |
| 1220 | data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; |
| 1221 | ast_moutdwm(ast, 0x1E6E0018, data); |
| 1222 | |
| 1223 | ast_moutdwm(ast, 0x1E6E0034, 0x00000001); |
| 1224 | ast_moutdwm(ast, 0x1E6E000C, 0x00000040); |
| 1225 | udelay(50); |
| 1226 | /* Mode Register Setting */ |
| 1227 | ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); |
| 1228 | ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); |
| 1229 | ast_moutdwm(ast, 0x1E6E0028, 0x00000005); |
| 1230 | ast_moutdwm(ast, 0x1E6E0028, 0x00000007); |
| 1231 | ast_moutdwm(ast, 0x1E6E0028, 0x00000003); |
| 1232 | ast_moutdwm(ast, 0x1E6E0028, 0x00000001); |
| 1233 | ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); |
| 1234 | ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); |
| 1235 | ast_moutdwm(ast, 0x1E6E0028, 0x00000001); |
| 1236 | |
| 1237 | ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); |
| 1238 | data = 0; |
| 1239 | if (param->wodt) { |
| 1240 | data = 0x300; |
| 1241 | } |
| 1242 | if (param->rodt) { |
| 1243 | data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); |
| 1244 | } |
| 1245 | ast_moutdwm(ast, 0x1E6E0034, data | 0x3); |
| 1246 | |
| 1247 | /* Calibrate the DQSI delay */ |
| 1248 | if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) |
| 1249 | goto ddr3_init_start; |
| 1250 | |
| 1251 | ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); |
| 1252 | /* ECC Memory Initialization */ |
| 1253 | #ifdef ECC |
| 1254 | ast_moutdwm(ast, 0x1E6E007C, 0x00000000); |
| 1255 | ast_moutdwm(ast, 0x1E6E0070, 0x221); |
| 1256 | timeout = 0; |
| 1257 | do { |
| 1258 | data = ast_mindwm(ast, 0x1E6E0070); |
| 1259 | timeout++; |
| 1260 | } while ((!(data & 0x00001000)) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1261 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1262 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1263 | ast_moutdwm(ast, 0x1E6E0070, 0x00000000); |
| 1264 | ast_moutdwm(ast, 0x1E6E0050, 0x80000000); |
| 1265 | ast_moutdwm(ast, 0x1E6E0050, 0x00000000); |
| 1266 | #endif |
| 1267 | |
| 1268 | |
| 1269 | } |
| 1270 | |
| 1271 | static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param) |
| 1272 | { |
| 1273 | u32 trap, trap_AC2, trap_MRS; |
| 1274 | |
| 1275 | ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); |
| 1276 | |
| 1277 | /* Ger trap info */ |
| 1278 | trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; |
| 1279 | trap_AC2 = (trap << 20) | (trap << 16); |
| 1280 | trap_AC2 += 0x00110000; |
| 1281 | trap_MRS = 0x00000040 | (trap << 4); |
| 1282 | |
| 1283 | |
| 1284 | param->reg_MADJ = 0x00034C4C; |
| 1285 | param->reg_SADJ = 0x00001800; |
| 1286 | param->reg_DRV = 0x000000F0; |
| 1287 | param->reg_PERIOD = param->dram_freq; |
| 1288 | param->rodt = 0; |
| 1289 | |
| 1290 | switch (param->dram_freq) { |
| 1291 | case 264: |
| 1292 | ast_moutdwm(ast, 0x1E6E2020, 0x0130); |
| 1293 | param->wodt = 0; |
| 1294 | param->reg_AC1 = 0x11101513; |
| 1295 | param->reg_AC2 = 0x78117011; |
| 1296 | param->reg_DQSIC = 0x00000092; |
| 1297 | param->reg_MRS = 0x00000842; |
| 1298 | param->reg_EMRS = 0x00000000; |
| 1299 | param->reg_DRV = 0x000000F0; |
| 1300 | param->reg_IOZ = 0x00000034; |
| 1301 | param->reg_DQIDLY = 0x0000005A; |
| 1302 | param->reg_FREQ = 0x00004AC0; |
| 1303 | param->madj_max = 138; |
| 1304 | param->dll2_finetune_step = 3; |
| 1305 | break; |
| 1306 | case 336: |
| 1307 | ast_moutdwm(ast, 0x1E6E2020, 0x0190); |
| 1308 | param->wodt = 1; |
| 1309 | param->reg_AC1 = 0x22202613; |
| 1310 | param->reg_AC2 = 0xAA009016 | trap_AC2; |
| 1311 | param->reg_DQSIC = 0x000000BA; |
| 1312 | param->reg_MRS = 0x00000A02 | trap_MRS; |
| 1313 | param->reg_EMRS = 0x00000040; |
| 1314 | param->reg_DRV = 0x000000FA; |
| 1315 | param->reg_IOZ = 0x00000034; |
| 1316 | param->reg_DQIDLY = 0x00000074; |
| 1317 | param->reg_FREQ = 0x00004DC0; |
| 1318 | param->madj_max = 96; |
| 1319 | param->dll2_finetune_step = 3; |
| 1320 | switch (param->dram_chipid) { |
| 1321 | default: |
| 1322 | case AST_DRAM_512Mx16: |
| 1323 | param->reg_AC2 = 0xAA009012 | trap_AC2; |
| 1324 | break; |
| 1325 | case AST_DRAM_1Gx16: |
| 1326 | param->reg_AC2 = 0xAA009016 | trap_AC2; |
| 1327 | break; |
| 1328 | case AST_DRAM_2Gx16: |
| 1329 | param->reg_AC2 = 0xAA009023 | trap_AC2; |
| 1330 | break; |
| 1331 | case AST_DRAM_4Gx16: |
| 1332 | param->reg_AC2 = 0xAA00903B | trap_AC2; |
| 1333 | break; |
| 1334 | } |
| 1335 | break; |
| 1336 | default: |
| 1337 | case 396: |
| 1338 | ast_moutdwm(ast, 0x1E6E2020, 0x03F1); |
| 1339 | param->wodt = 1; |
| 1340 | param->rodt = 0; |
| 1341 | param->reg_AC1 = 0x33302714; |
| 1342 | param->reg_AC2 = 0xCC00B01B | trap_AC2; |
| 1343 | param->reg_DQSIC = 0x000000E2; |
| 1344 | param->reg_MRS = 0x00000C02 | trap_MRS; |
| 1345 | param->reg_EMRS = 0x00000040; |
| 1346 | param->reg_DRV = 0x000000FA; |
| 1347 | param->reg_IOZ = 0x00000034; |
| 1348 | param->reg_DQIDLY = 0x00000089; |
| 1349 | param->reg_FREQ = 0x00005040; |
| 1350 | param->madj_max = 96; |
| 1351 | param->dll2_finetune_step = 4; |
| 1352 | |
| 1353 | switch (param->dram_chipid) { |
| 1354 | case AST_DRAM_512Mx16: |
| 1355 | param->reg_AC2 = 0xCC00B016 | trap_AC2; |
| 1356 | break; |
| 1357 | default: |
| 1358 | case AST_DRAM_1Gx16: |
| 1359 | param->reg_AC2 = 0xCC00B01B | trap_AC2; |
| 1360 | break; |
| 1361 | case AST_DRAM_2Gx16: |
| 1362 | param->reg_AC2 = 0xCC00B02B | trap_AC2; |
| 1363 | break; |
| 1364 | case AST_DRAM_4Gx16: |
| 1365 | param->reg_AC2 = 0xCC00B03F | trap_AC2; |
| 1366 | break; |
| 1367 | } |
| 1368 | |
| 1369 | break; |
| 1370 | |
| 1371 | case 408: |
| 1372 | ast_moutdwm(ast, 0x1E6E2020, 0x01F0); |
| 1373 | param->wodt = 1; |
| 1374 | param->rodt = 0; |
| 1375 | param->reg_AC1 = 0x33302714; |
| 1376 | param->reg_AC2 = 0xCC00B01B | trap_AC2; |
| 1377 | param->reg_DQSIC = 0x000000E2; |
| 1378 | param->reg_MRS = 0x00000C02 | trap_MRS; |
| 1379 | param->reg_EMRS = 0x00000040; |
| 1380 | param->reg_DRV = 0x000000FA; |
| 1381 | param->reg_IOZ = 0x00000034; |
| 1382 | param->reg_DQIDLY = 0x00000089; |
| 1383 | param->reg_FREQ = 0x000050C0; |
| 1384 | param->madj_max = 96; |
| 1385 | param->dll2_finetune_step = 4; |
| 1386 | |
| 1387 | switch (param->dram_chipid) { |
| 1388 | case AST_DRAM_512Mx16: |
| 1389 | param->reg_AC2 = 0xCC00B016 | trap_AC2; |
| 1390 | break; |
| 1391 | default: |
| 1392 | case AST_DRAM_1Gx16: |
| 1393 | param->reg_AC2 = 0xCC00B01B | trap_AC2; |
| 1394 | break; |
| 1395 | case AST_DRAM_2Gx16: |
| 1396 | param->reg_AC2 = 0xCC00B02B | trap_AC2; |
| 1397 | break; |
| 1398 | case AST_DRAM_4Gx16: |
| 1399 | param->reg_AC2 = 0xCC00B03F | trap_AC2; |
| 1400 | break; |
| 1401 | } |
| 1402 | |
| 1403 | break; |
| 1404 | case 456: |
| 1405 | ast_moutdwm(ast, 0x1E6E2020, 0x0230); |
| 1406 | param->wodt = 0; |
| 1407 | param->reg_AC1 = 0x33302815; |
| 1408 | param->reg_AC2 = 0xCD44B01E; |
| 1409 | param->reg_DQSIC = 0x000000FC; |
| 1410 | param->reg_MRS = 0x00000E72; |
| 1411 | param->reg_EMRS = 0x00000000; |
| 1412 | param->reg_DRV = 0x00000000; |
| 1413 | param->reg_IOZ = 0x00000034; |
| 1414 | param->reg_DQIDLY = 0x00000097; |
| 1415 | param->reg_FREQ = 0x000052C0; |
| 1416 | param->madj_max = 88; |
| 1417 | param->dll2_finetune_step = 3; |
| 1418 | break; |
| 1419 | case 504: |
| 1420 | ast_moutdwm(ast, 0x1E6E2020, 0x0261); |
| 1421 | param->wodt = 1; |
| 1422 | param->rodt = 1; |
| 1423 | param->reg_AC1 = 0x33302815; |
| 1424 | param->reg_AC2 = 0xDE44C022; |
| 1425 | param->reg_DQSIC = 0x00000117; |
| 1426 | param->reg_MRS = 0x00000E72; |
| 1427 | param->reg_EMRS = 0x00000040; |
| 1428 | param->reg_DRV = 0x0000000A; |
| 1429 | param->reg_IOZ = 0x00000045; |
| 1430 | param->reg_DQIDLY = 0x000000A0; |
| 1431 | param->reg_FREQ = 0x000054C0; |
| 1432 | param->madj_max = 79; |
| 1433 | param->dll2_finetune_step = 3; |
| 1434 | break; |
| 1435 | case 528: |
| 1436 | ast_moutdwm(ast, 0x1E6E2020, 0x0120); |
| 1437 | param->wodt = 1; |
| 1438 | param->rodt = 1; |
| 1439 | param->reg_AC1 = 0x33302815; |
| 1440 | param->reg_AC2 = 0xEF44D024; |
| 1441 | param->reg_DQSIC = 0x00000125; |
| 1442 | param->reg_MRS = 0x00000E72; |
| 1443 | param->reg_EMRS = 0x00000004; |
| 1444 | param->reg_DRV = 0x000000F9; |
| 1445 | param->reg_IOZ = 0x00000045; |
| 1446 | param->reg_DQIDLY = 0x000000A7; |
| 1447 | param->reg_FREQ = 0x000055C0; |
| 1448 | param->madj_max = 76; |
| 1449 | param->dll2_finetune_step = 3; |
| 1450 | break; |
| 1451 | case 552: |
| 1452 | ast_moutdwm(ast, 0x1E6E2020, 0x02A1); |
| 1453 | param->wodt = 1; |
| 1454 | param->rodt = 1; |
| 1455 | param->reg_AC1 = 0x43402915; |
| 1456 | param->reg_AC2 = 0xFF44E025; |
| 1457 | param->reg_DQSIC = 0x00000132; |
| 1458 | param->reg_MRS = 0x00000E72; |
| 1459 | param->reg_EMRS = 0x00000040; |
| 1460 | param->reg_DRV = 0x0000000A; |
| 1461 | param->reg_IOZ = 0x00000045; |
| 1462 | param->reg_DQIDLY = 0x000000AD; |
| 1463 | param->reg_FREQ = 0x000056C0; |
| 1464 | param->madj_max = 76; |
| 1465 | param->dll2_finetune_step = 3; |
| 1466 | break; |
| 1467 | case 576: |
| 1468 | ast_moutdwm(ast, 0x1E6E2020, 0x0140); |
| 1469 | param->wodt = 1; |
| 1470 | param->rodt = 1; |
| 1471 | param->reg_AC1 = 0x43402915; |
| 1472 | param->reg_AC2 = 0xFF44E027; |
| 1473 | param->reg_DQSIC = 0x0000013F; |
| 1474 | param->reg_MRS = 0x00000E72; |
| 1475 | param->reg_EMRS = 0x00000004; |
| 1476 | param->reg_DRV = 0x000000F5; |
| 1477 | param->reg_IOZ = 0x00000045; |
| 1478 | param->reg_DQIDLY = 0x000000B3; |
| 1479 | param->reg_FREQ = 0x000057C0; |
| 1480 | param->madj_max = 76; |
| 1481 | param->dll2_finetune_step = 3; |
| 1482 | break; |
| 1483 | } |
| 1484 | |
| 1485 | switch (param->dram_chipid) { |
| 1486 | case AST_DRAM_512Mx16: |
| 1487 | param->dram_config = 0x100; |
| 1488 | break; |
| 1489 | default: |
| 1490 | case AST_DRAM_1Gx16: |
| 1491 | param->dram_config = 0x121; |
| 1492 | break; |
| 1493 | case AST_DRAM_2Gx16: |
| 1494 | param->dram_config = 0x122; |
| 1495 | break; |
| 1496 | case AST_DRAM_4Gx16: |
| 1497 | param->dram_config = 0x123; |
| 1498 | break; |
| 1499 | } /* switch size */ |
| 1500 | |
| 1501 | switch (param->vram_size) { |
| 1502 | default: |
| 1503 | case AST_VIDMEM_SIZE_8M: |
| 1504 | param->dram_config |= 0x00; |
| 1505 | break; |
| 1506 | case AST_VIDMEM_SIZE_16M: |
| 1507 | param->dram_config |= 0x04; |
| 1508 | break; |
| 1509 | case AST_VIDMEM_SIZE_32M: |
| 1510 | param->dram_config |= 0x08; |
| 1511 | break; |
| 1512 | case AST_VIDMEM_SIZE_64M: |
| 1513 | param->dram_config |= 0x0c; |
| 1514 | break; |
| 1515 | } |
| 1516 | } |
| 1517 | |
| 1518 | static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param) |
| 1519 | { |
| 1520 | u32 data, data2, retry = 0; |
| 1521 | uint32_t timeout; |
| 1522 | uint32_t timeout2; |
| 1523 | |
| 1524 | ddr2_init_start: |
| 1525 | ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); |
| 1526 | ast_moutdwm(ast, 0x1E6E0018, 0x00000100); |
| 1527 | ast_moutdwm(ast, 0x1E6E0024, 0x00000000); |
| 1528 | ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); |
| 1529 | ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); |
| 1530 | udelay(10); |
| 1531 | ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); |
| 1532 | udelay(10); |
| 1533 | |
| 1534 | ast_moutdwm(ast, 0x1E6E0004, param->dram_config); |
| 1535 | ast_moutdwm(ast, 0x1E6E0008, 0x90040f); |
| 1536 | ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); |
| 1537 | ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); |
| 1538 | ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); |
| 1539 | ast_moutdwm(ast, 0x1E6E0080, 0x00000000); |
| 1540 | ast_moutdwm(ast, 0x1E6E0084, 0x00000000); |
| 1541 | ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); |
| 1542 | ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); |
| 1543 | ast_moutdwm(ast, 0x1E6E0018, 0x00002330); |
| 1544 | ast_moutdwm(ast, 0x1E6E0038, 0x00000000); |
| 1545 | ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); |
| 1546 | ast_moutdwm(ast, 0x1E6E0044, 0x88848466); |
| 1547 | ast_moutdwm(ast, 0x1E6E0048, 0x44440008); |
| 1548 | ast_moutdwm(ast, 0x1E6E004C, 0x00000000); |
| 1549 | ast_moutdwm(ast, 0x1E6E0050, 0x80000000); |
| 1550 | ast_moutdwm(ast, 0x1E6E0050, 0x00000000); |
| 1551 | ast_moutdwm(ast, 0x1E6E0054, 0); |
| 1552 | ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); |
| 1553 | ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); |
| 1554 | ast_moutdwm(ast, 0x1E6E0070, 0x00000000); |
| 1555 | ast_moutdwm(ast, 0x1E6E0074, 0x00000000); |
| 1556 | ast_moutdwm(ast, 0x1E6E0078, 0x00000000); |
| 1557 | ast_moutdwm(ast, 0x1E6E007C, 0x00000000); |
| 1558 | |
| 1559 | /* Wait MCLK2X lock to MCLK */ |
| 1560 | timeout = 0; |
| 1561 | do { |
| 1562 | data = ast_mindwm(ast, 0x1E6E001C); |
| 1563 | timeout++; |
| 1564 | } while ((!(data & 0x08000000)) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1565 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1566 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1567 | data = ast_mindwm(ast, 0x1E6E001C); |
| 1568 | data = (data >> 8) & 0xff; |
| 1569 | timeout = 0; |
| 1570 | while (((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)) { |
| 1571 | data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; |
| 1572 | if ((data2 & 0xff) > param->madj_max) { |
| 1573 | break; |
| 1574 | } |
| 1575 | ast_moutdwm(ast, 0x1E6E0064, data2); |
| 1576 | if (data2 & 0x00100000) { |
| 1577 | data2 = ((data2 & 0xff) >> 3) + 3; |
| 1578 | } else { |
| 1579 | data2 = ((data2 & 0xff) >> 2) + 5; |
| 1580 | } |
| 1581 | data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; |
| 1582 | data2 += data & 0xff; |
| 1583 | data = data | (data2 << 8); |
| 1584 | ast_moutdwm(ast, 0x1E6E0068, data); |
| 1585 | udelay(10); |
| 1586 | ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); |
| 1587 | udelay(10); |
| 1588 | data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; |
| 1589 | ast_moutdwm(ast, 0x1E6E0018, data); |
| 1590 | data = data | 0x200; |
| 1591 | ast_moutdwm(ast, 0x1E6E0018, data); |
| 1592 | timeout2 = 0; |
| 1593 | do { |
| 1594 | data = ast_mindwm(ast, 0x1E6E001C); |
| 1595 | timeout2++; |
| 1596 | } while ((!(data & 0x08000000)) && (timeout2 < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1597 | if (timeout2 >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1598 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1599 | |
| 1600 | data = ast_mindwm(ast, 0x1E6E001C); |
| 1601 | data = (data >> 8) & 0xff; |
| 1602 | |
| 1603 | timeout++; |
| 1604 | } |
| 1605 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1606 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1607 | ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); |
| 1608 | data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; |
| 1609 | ast_moutdwm(ast, 0x1E6E0018, data); |
| 1610 | |
| 1611 | ast_moutdwm(ast, 0x1E6E0034, 0x00000001); |
| 1612 | ast_moutdwm(ast, 0x1E6E000C, 0x00000000); |
| 1613 | udelay(50); |
| 1614 | /* Mode Register Setting */ |
| 1615 | ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); |
| 1616 | ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); |
| 1617 | ast_moutdwm(ast, 0x1E6E0028, 0x00000005); |
| 1618 | ast_moutdwm(ast, 0x1E6E0028, 0x00000007); |
| 1619 | ast_moutdwm(ast, 0x1E6E0028, 0x00000003); |
| 1620 | ast_moutdwm(ast, 0x1E6E0028, 0x00000001); |
| 1621 | |
| 1622 | ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); |
| 1623 | ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); |
| 1624 | ast_moutdwm(ast, 0x1E6E0028, 0x00000001); |
| 1625 | ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); |
| 1626 | ast_moutdwm(ast, 0x1E6E0028, 0x00000003); |
| 1627 | ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); |
| 1628 | ast_moutdwm(ast, 0x1E6E0028, 0x00000003); |
| 1629 | |
| 1630 | ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); |
| 1631 | data = 0; |
| 1632 | if (param->wodt) { |
| 1633 | data = 0x500; |
| 1634 | } |
| 1635 | if (param->rodt) { |
| 1636 | data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); |
| 1637 | } |
| 1638 | ast_moutdwm(ast, 0x1E6E0034, data | 0x3); |
| 1639 | ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); |
| 1640 | |
| 1641 | /* Calibrate the DQSI delay */ |
| 1642 | if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) |
| 1643 | goto ddr2_init_start; |
| 1644 | |
| 1645 | /* ECC Memory Initialization */ |
| 1646 | #ifdef ECC |
| 1647 | ast_moutdwm(ast, 0x1E6E007C, 0x00000000); |
| 1648 | ast_moutdwm(ast, 0x1E6E0070, 0x221); |
| 1649 | timeout = 0; |
| 1650 | do { |
| 1651 | data = ast_mindwm(ast, 0x1E6E0070); |
| 1652 | timeout++; |
| 1653 | } while ((!(data & 0x00001000)) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1654 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1655 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1656 | ast_moutdwm(ast, 0x1E6E0070, 0x00000000); |
| 1657 | ast_moutdwm(ast, 0x1E6E0050, 0x80000000); |
| 1658 | ast_moutdwm(ast, 0x1E6E0050, 0x00000000); |
| 1659 | #endif |
| 1660 | |
| 1661 | } |
| 1662 | |
| 1663 | static void ast_init_dram_2300(struct drm_device *dev) |
| 1664 | { |
| 1665 | struct ast_private *ast = dev->dev_private; |
| 1666 | struct ast2300_dram_param param; |
| 1667 | u32 temp; |
| 1668 | u8 reg; |
| 1669 | uint32_t timeout; |
| 1670 | |
| 1671 | reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); |
| 1672 | if ((reg & 0x80) == 0) {/* vga only */ |
| 1673 | ast_write32(ast, 0xf004, 0x1e6e0000); |
| 1674 | ast_write32(ast, 0xf000, 0x1); |
| 1675 | ast_write32(ast, 0x12000, 0x1688a8a8); |
| 1676 | timeout = 0; |
| 1677 | do { |
| 1678 | timeout++; |
| 1679 | } while ((ast_read32(ast, 0x12000) != 0x1) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1680 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1681 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1682 | |
| 1683 | ast_write32(ast, 0x10000, 0xfc600309); |
| 1684 | timeout = 0; |
| 1685 | do { |
| 1686 | timeout++; |
| 1687 | } while ((ast_read32(ast, 0x10000) != 0x1) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1688 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1689 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1690 | |
| 1691 | /* Slow down CPU/AHB CLK in VGA only mode */ |
| 1692 | temp = ast_read32(ast, 0x12008); |
| 1693 | temp |= 0x73; |
| 1694 | ast_write32(ast, 0x12008, temp); |
| 1695 | |
| 1696 | param.dram_type = AST_DDR3; |
| 1697 | if (temp & 0x01000000) |
| 1698 | param.dram_type = AST_DDR2; |
| 1699 | param.dram_chipid = ast->dram_type; |
| 1700 | param.dram_freq = ast->mclk; |
| 1701 | param.vram_size = ast->vram_size; |
| 1702 | |
| 1703 | if (param.dram_type == AST_DDR3) { |
| 1704 | get_ddr3_info(ast, ¶m); |
| 1705 | ddr3_init(ast, ¶m); |
| 1706 | } else { |
| 1707 | get_ddr2_info(ast, ¶m); |
| 1708 | ddr2_init(ast, ¶m); |
| 1709 | } |
| 1710 | |
| 1711 | temp = ast_mindwm(ast, 0x1e6e2040); |
| 1712 | ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); |
| 1713 | } |
| 1714 | |
| 1715 | /* wait ready */ |
| 1716 | timeout = 0; |
| 1717 | do { |
| 1718 | reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); |
| 1719 | timeout++; |
| 1720 | } while (((reg & 0x40) == 0) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT)); |
| 1721 | if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) |
| 1722 | dev_err(dev->pdev, "Timeout while waiting for register\n"); |
| 1723 | } |
| 1724 | |