Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
Angel Pons | 0515aa1 | 2021-10-15 14:22:30 +0200 | [diff] [blame] | 2 | # FSP configuration |
| 3 | |
| 4 | register "SataMode" = "0" # AHCI |
| 5 | register "SataSalpSupport" = "0" |
| 6 | register "satapwroptimize" = "1" |
| 7 | register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1 |
| 8 | |
| 9 | register "SataPortsEnable[0]" = "1" |
| 10 | register "SataPortsEnable[1]" = "1" # depends on SATAXPCIE1 |
| 11 | register "SataPortsEnable[2]" = "0" # Not used for SATA |
| 12 | register "SataPortsEnable[3]" = "0" # Not used for SATA |
| 13 | register "SataPortsEnable[4]" = "1" |
| 14 | register "SataPortsEnable[5]" = "1" |
| 15 | register "SataPortsEnable[6]" = "1" |
| 16 | register "SataPortsEnable[7]" = "1" |
| 17 | |
| 18 | register "SataPortsHotPlug[0]" = "1" |
| 19 | register "SataPortsHotPlug[1]" = "1" |
| 20 | register "SataPortsHotPlug[2]" = "0" |
| 21 | register "SataPortsHotPlug[3]" = "0" |
| 22 | register "SataPortsHotPlug[4]" = "1" |
| 23 | register "SataPortsHotPlug[5]" = "1" |
| 24 | register "SataPortsHotPlug[6]" = "1" |
| 25 | register "SataPortsHotPlug[7]" = "1" |
| 26 | |
| 27 | register "PchHdaDspEnable" = "0" |
| 28 | register "PchHdaAudioLinkHda" = "1" |
| 29 | |
Angel Pons | 1bfabb0 | 2021-10-15 15:11:38 +0200 | [diff] [blame] | 30 | register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # PCIe Slot1 |
| 31 | register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # PCIe Slot2 |
| 32 | register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" # PCIe Slot4 |
| 33 | register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" # PCIe Slot6 |
Angel Pons | 0515aa1 | 2021-10-15 14:22:30 +0200 | [diff] [blame] | 34 | register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # RP9 M2 Slot M x4 |
| 35 | register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # RP16 M2 Slot E x1 |
Angel Pons | 1bfabb0 | 2021-10-15 15:11:38 +0200 | [diff] [blame] | 36 | register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # BMC |
| 37 | register "PcieClkSrcUsage[7]" = "PCIE_CLK_FREE" # PHY 3 |
| 38 | register "PcieClkSrcUsage[8]" = "PCIE_CLK_FREE" # PCIe Slot3 |
| 39 | register "PcieClkSrcUsage[9]" = "PCIE_CLK_FREE" # PHY 4 |
| 40 | register "PcieClkSrcUsage[10]" = "PCIE_CLK_FREE" # PHY 2 |
| 41 | register "PcieClkSrcUsage[11]" = "PCIE_CLK_FREE" # PHY 1 |
| 42 | register "PcieClkSrcUsage[12]" = "PCIE_CLK_FREE" # PHY 0 |
| 43 | register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE" # PB |
| 44 | register "PcieClkSrcUsage[14]" = "PCIE_CLK_NOTUSED" |
| 45 | register "PcieClkSrcUsage[15]" = "PCIE_CLK_NOTUSED" |
Angel Pons | 0515aa1 | 2021-10-15 14:22:30 +0200 | [diff] [blame] | 46 | |
| 47 | # Only map M2 CLKREQ to CLK gen |
| 48 | register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n |
| 49 | register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n |
| 50 | |
| 51 | # USB OC5-7: not connected |
| 52 | register "usb2_ports" = "{ |
| 53 | |
| 54 | #define HERMES_USB2_CONFIG(pin) { \ |
| 55 | .enable = 1, \ |
| 56 | .ocpin = (pin), \ |
| 57 | .tx_bias = USB2_BIAS_0MV, \ |
| 58 | .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ |
| 59 | .pre_emp_bias = USB2_BIAS_28P15MV, \ |
| 60 | .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ |
| 61 | } |
| 62 | [0] = HERMES_USB2_CONFIG(OC0), /* USB3 rear panel 1 */ |
| 63 | [1] = HERMES_USB2_CONFIG(OC0), |
| 64 | [2] = HERMES_USB2_CONFIG(OC1), /* USB3 rear panel 2 */ |
| 65 | [3] = HERMES_USB2_CONFIG(OC1), |
| 66 | [4] = HERMES_USB2_CONFIG(OC2), /* USB3 internal header CN_USB3_HDR */ |
| 67 | [5] = HERMES_USB2_CONFIG(OC2), |
| 68 | [6] = HERMES_USB2_CONFIG(OC3), /* USB2 internal header USB2_HDR1 */ |
| 69 | [7] = HERMES_USB2_CONFIG(OC3), |
| 70 | [8] = HERMES_USB2_CONFIG(OC4), /* USB2 internal header USB2_HDR1 */ |
| 71 | [9] = HERMES_USB2_CONFIG(OC4), |
| 72 | [10] = HERMES_USB2_CONFIG(OC_SKIP), /* BMC */ |
| 73 | [11] = USB2_PORT_EMPTY, |
| 74 | [12] = HERMES_USB2_CONFIG(OC_SKIP), /* piggy-back */ |
| 75 | [13] = HERMES_USB2_CONFIG(OC_SKIP), /* M.2 key E */ |
| 76 | }" |
| 77 | |
| 78 | # USB Config 2.0/3.0 |
| 79 | # Enumeration starts at 0 |
| 80 | # USB 3.0 |
| 81 | # USB OC0: RP1 |
| 82 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" |
| 83 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" |
| 84 | |
| 85 | # USB OC1: RP2 |
| 86 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" |
| 87 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" |
| 88 | |
| 89 | # USB OC2: Internal Header CN_USB3_HDR |
| 90 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" |
| 91 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" |
| 92 | |
| 93 | # Thermal |
| 94 | register "tcc_offset" = "1" # TCC of 99C |
| 95 | |
| 96 | # Disable S0ix |
| 97 | register "s0ix_enable" = "0" |
| 98 | |
| 99 | # Enable Turbo |
| 100 | register "eist_enable" = "1" |
| 101 | |
| 102 | register "common_soc_config" = "{ |
| 103 | .gspi[0] = { |
| 104 | .speed_mhz = 1, |
| 105 | .early_init = 1, |
| 106 | }, |
| 107 | }" |
| 108 | |
| 109 | # VR Power Delivery Design |
| 110 | register "VrPowerDeliveryDesign" = "0x12" |
| 111 | |
| 112 | register "SerialIoDevMode" = "{ |
| 113 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 114 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 115 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 116 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 117 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 118 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 119 | [PchSerialIoIndexSPI0] = PchSerialIoPci, |
| 120 | [PchSerialIoIndexSPI1] = PchSerialIoDisabled, |
| 121 | [PchSerialIoIndexUART0] = PchSerialIoPci, |
| 122 | [PchSerialIoIndexUART1] = PchSerialIoPci, |
| 123 | [PchSerialIoIndexUART2] = PchSerialIoPci, |
| 124 | }" |
| 125 | |
| 126 | register "DisableHeciRetry" = "1" |
| 127 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 128 | device cpu_cluster 0 on |
| 129 | device lapic 0 on end |
| 130 | end |
| 131 | |
| 132 | device domain 0 on |
| 133 | device pci 00.0 on end # Host Bridge |
| 134 | device pci 01.0 on # PEG x8 / Slot 2 |
| 135 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT2" "SlotDataBusWidth8X" |
| 136 | end |
| 137 | device pci 01.1 on # PEG x4 or x8 / Slot 6 |
| 138 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT6" "SlotDataBusWidth4X" |
| 139 | end |
| 140 | device pci 01.2 on # PEG x4 or disabled / Slot 4 |
| 141 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X" |
| 142 | end |
Angel Pons | 0515aa1 | 2021-10-15 14:22:30 +0200 | [diff] [blame] | 143 | device pci 02.0 on end # Integrated Graphics Device |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 144 | device pci 04.0 on end # SA Thermal device |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 145 | device pci 08.0 on end # Gaussian Mixture |
| 146 | device pci 12.0 on end # Thermal Subsystem |
| 147 | device pci 14.0 on end # USB xHCI |
Patrick Rudolph | ae758fa | 2020-06-18 11:34:19 +0200 | [diff] [blame] | 148 | device pci 14.1 off end # USB xDCI (OTG) |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 149 | device pci 14.2 on end # RAM controller |
Angel Pons | 0515aa1 | 2021-10-15 14:22:30 +0200 | [diff] [blame] | 150 | device pci 14.3 on |
| 151 | chip drivers/wifi/generic |
| 152 | register "wake" = "PME_B0_EN_BIT" |
| 153 | device generic 0 on end |
| 154 | end |
| 155 | end # CNVi wifi |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 156 | device pci 14.5 off end # SDCard |
Michael Niewöhner | 50a1072 | 2020-11-04 00:19:28 +0100 | [diff] [blame] | 157 | device pci 16.0 on end # Management Engine Interface 1 |
Felix Singer | 250a7ac | 2020-07-26 21:19:21 +0200 | [diff] [blame] | 158 | device pci 16.1 on end # Management Engine Interface 2 |
Felix Singer | d9e4594 | 2020-08-19 14:13:15 +0200 | [diff] [blame] | 159 | device pci 16.4 off end # Management Engine Interface 3 |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 160 | device pci 17.0 on end # SATA |
Angel Pons | 0515aa1 | 2021-10-15 14:22:30 +0200 | [diff] [blame] | 161 | # This device does not have any function on CNP-H, but it needs |
| 162 | # to be here so that the resource allocator is aware of UART 2. |
| 163 | device pci 19.0 hidden end |
| 164 | chip soc/intel/common/block/uart |
| 165 | device pci 19.2 hidden |
| 166 | register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2" |
| 167 | end # UART #2, in ACPI mode |
| 168 | end |
| 169 | device pci 1b.4 on # PCIe root port 21 (Slot 1) |
| 170 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" |
| 171 | register "PcieRpEnable[20]" = "1" |
| 172 | register "PcieRpLtrEnable[20]" = "1" |
| 173 | register "PcieRpSlotImplemented[20]" = "1" |
| 174 | register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" |
| 175 | register "PcieRpAdvancedErrorReporting[20]" = "1" |
| 176 | register "PcieRpAspm[20]" = "AspmDisabled" |
| 177 | end |
| 178 | device pci 1c.0 on # PCIe root port 1 (Slot 3) |
| 179 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" |
| 180 | register "PcieRpEnable[0]" = "1" |
| 181 | register "PcieRpLtrEnable[0]" = "1" |
| 182 | register "PcieRpSlotImplemented[0]" = "1" |
| 183 | register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" |
| 184 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 185 | register "PcieRpAspm[0]" = "AspmDisabled" |
| 186 | end |
| 187 | device pci 1c.4 on # PCIe root port 5 (PHY 3) |
| 188 | register "PcieRpEnable[4]" = "1" |
| 189 | end |
| 190 | device pci 1c.5 on # PCIe root port 6 (PHY 4) |
| 191 | register "PcieRpEnable[5]" = "1" |
| 192 | end |
| 193 | device pci 1c.6 on # PCIe root port 7 (PHY 2) |
| 194 | register "PcieRpEnable[6]" = "1" |
| 195 | end |
| 196 | device pci 1c.7 on # PCIe root port 8 (PHY 1) |
| 197 | register "PcieRpEnable[7]" = "1" |
| 198 | end |
| 199 | device pci 1d.0 on # PCIe root port 9 (M2 M) |
| 200 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" |
| 201 | register "PcieRpEnable[8]" = "1" |
| 202 | register "PcieRpSlotImplemented[8]" = "1" |
| 203 | end |
| 204 | device pci 1d.5 on # PCIe root port 14 (PHY 0) |
| 205 | register "PcieRpEnable[13]" = "1" |
| 206 | end |
| 207 | device pci 1d.6 on # PCIe root port 15 (BMC) |
| 208 | device pci 00.0 on # Aspeed PCI Bridge |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 209 | device pci 00.0 on end # Aspeed 2500 VGA |
| 210 | end |
Angel Pons | 0515aa1 | 2021-10-15 14:22:30 +0200 | [diff] [blame] | 211 | register "PcieRpEnable[14]" = "1" |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 212 | register "PcieRpSlotImplemented[14]" = "1" |
Felix Singer | 2b9035e | 2020-08-18 23:12:55 +0200 | [diff] [blame] | 213 | end |
Angel Pons | 0515aa1 | 2021-10-15 14:22:30 +0200 | [diff] [blame] | 214 | device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) |
| 215 | # Disabled when CNVi is present |
| 216 | register "PcieRpEnable[15]" = "1" |
| 217 | register "PcieRpSlotImplemented[15]" = "1" |
| 218 | end |
| 219 | device pci 1e.0 on end # UART #0 |
| 220 | device pci 1e.1 on end # UART #1 |
| 221 | device pci 1e.2 off end # GSPI #0 |
| 222 | device pci 1e.3 off end # GSPI #1 |
Elyes HAOUAS | bda27cd | 2020-06-27 07:17:16 +0200 | [diff] [blame] | 223 | device pci 1f.0 on # LPC Interface |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 224 | chip drivers/pc80/tpm |
| 225 | device pnp 0c31.0 on end |
| 226 | end |
| 227 | # AST2500, but not enabled to decode LPC cycles |
| 228 | end |
Patrick Rudolph | 63df43d | 2021-09-11 08:17:39 +0200 | [diff] [blame] | 229 | device pci 1f.1 on end # P2SB |
| 230 | device pci 1f.2 hidden end # Power Management Controller |
| 231 | device pci 1f.3 on end # Intel HDA |
| 232 | device pci 1f.4 on end # SMBus |
| 233 | device pci 1f.5 on end # PCH SPI |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 234 | end |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 235 | end |