Robert Zieba | 5a040d6 | 2022-10-03 14:27:16 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef AMD_BLOCK_PCI_GPP_H |
| 4 | #define AMD_BLOCK_PCI_GPP_H |
| 5 | |
Felix Held | 968a58d | 2024-02-01 19:51:57 +0100 | [diff] [blame] | 6 | #include <types.h> |
Robert Zieba | 5a040d6 | 2022-10-03 14:27:16 -0600 | [diff] [blame] | 7 | |
Varshit Pandya | 0452d09 | 2024-02-08 21:32:57 +0530 | [diff] [blame^] | 8 | /* FCH MISC Registers 0xfed80e00 */ |
| 9 | #define GPP_CLK_CNTRL 0x00 |
| 10 | #define GPP_CLK0_REQ_SHIFT 0 |
| 11 | #define GPP_CLK1_REQ_SHIFT 2 |
| 12 | #define GPP_CLK4_REQ_SHIFT 4 |
| 13 | #define GPP_CLK2_REQ_SHIFT 6 |
| 14 | #define GPP_CLK3_REQ_SHIFT 8 |
| 15 | #define GPP_CLK5_REQ_SHIFT 10 |
| 16 | #define GPP_CLK6_REQ_SHIFT 12 |
| 17 | #define GPP_CLK_OUTPUT_COUNT 7 |
| 18 | #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) |
| 19 | #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) |
| 20 | #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) |
| 21 | #define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift)) |
| 22 | |
Robert Zieba | 5a040d6 | 2022-10-03 14:27:16 -0600 | [diff] [blame] | 23 | enum gpp_clk_req { |
| 24 | GPP_CLK_ON, /* GPP clock always on; default */ |
| 25 | GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ |
| 26 | GPP_CLK_OFF, /* GPP clk off */ |
| 27 | }; |
| 28 | |
| 29 | void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, |
| 30 | size_t gpp_clk_config_num); |
| 31 | |
Varshit Pandya | 0452d09 | 2024-02-08 21:32:57 +0530 | [diff] [blame^] | 32 | /* configure the general purpose PCIe clock outputs according to the devicetree settings */ |
| 33 | void gpp_clk_setup_common(enum gpp_clk_req *gpp_clk_config, |
| 34 | size_t gpp_clk_config_num); |
| 35 | |
Robert Zieba | 5a040d6 | 2022-10-03 14:27:16 -0600 | [diff] [blame] | 36 | #endif |