Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 1 | #include <stdlib.h> |
| 2 | #include <string.h> |
| 3 | #include <stddef.h> |
| 4 | #include <delay.h> |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 7 | #include <cbmem.h> |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 8 | #include <arch/cache.h> |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 9 | #include <cpu/samsung/exynos5250/fimd.h> |
| 10 | #include <cpu/samsung/exynos5-common/s5p-dp-core.h> |
| 11 | #include "chip.h" |
| 12 | #include "cpu.h" |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 13 | |
David Hendricks | 0f5a3fc | 2013-03-12 20:16:44 -0700 | [diff] [blame] | 14 | #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) |
| 15 | #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 16 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 17 | /* we distinguish a display port device from a raw graphics device |
| 18 | * because there are dramatic differences in startup depending on |
| 19 | * graphics usage. To make startup fast and easier to understand and |
| 20 | * debug we explicitly name this common case. The alternate approach, |
| 21 | * involving lots of machine and callbacks, is hard to debug and |
| 22 | * verify. |
| 23 | */ |
| 24 | static void exynos_displayport_init(device_t dev) |
| 25 | { |
| 26 | int ret; |
| 27 | struct cpu_samsung_exynos5250_config *conf = dev->chip_info; |
| 28 | /* put these on the stack. If, at some point, we want to move |
| 29 | * this code to a pre-ram stage, it will be much easier. |
| 30 | */ |
| 31 | vidinfo_t vi; |
| 32 | struct exynos5_fimd_panel panel; |
| 33 | unsigned long int fb_size; |
| 34 | u32 lcdbase; |
| 35 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 36 | memset(&vi, 0, sizeof(vi)); |
| 37 | memset(&panel, 0, sizeof(panel)); |
| 38 | |
| 39 | panel.is_dp = 1; /* Display I/F is eDP */ |
| 40 | /* while it is true that we did a memset to zero, |
| 41 | * we leave some 'set to zero' entries here to make |
| 42 | * it clear what's going on. Graphics is confusing. |
| 43 | */ |
| 44 | panel.is_mipi = 0; |
| 45 | panel.fixvclk = 0; |
| 46 | panel.ivclk = 0; |
| 47 | panel.clkval_f = conf->clkval_f; |
| 48 | panel.upper_margin = conf->upper_margin; |
| 49 | panel.lower_margin = conf->lower_margin; |
| 50 | panel.vsync = conf->vsync; |
| 51 | panel.left_margin = conf->left_margin; |
| 52 | panel.right_margin = conf->right_margin; |
| 53 | panel.hsync = conf->hsync; |
Ronald G. Minnich | d83c117 | 2013-04-18 16:10:29 -0700 | [diff] [blame] | 54 | panel.xres = conf->xres; |
| 55 | panel.yres = conf->yres; |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 56 | |
| 57 | vi.vl_col = conf->xres; |
| 58 | vi.vl_row = conf->yres; |
| 59 | vi.vl_bpix = conf->bpp; |
| 60 | /* |
| 61 | * The size is a magic number from hardware. Allocate enough for the |
| 62 | * frame buffer and color map. |
| 63 | */ |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 64 | fb_size = conf->xres * conf->yres * (conf->bpp / 8); |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 65 | lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); |
| 66 | printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase)); |
| 67 | mmio_resource(dev, 0, lcdbase/KiB, 64); |
| 68 | vi.cmap = (void *)lcdbase; |
| 69 | |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 70 | /* |
| 71 | * We need to clean and invalidate the framebuffer region and disable |
| 72 | * caching as well. We assume that our dcache <--> memory address |
| 73 | * space is identity-mapped in 1MB chunks, so align accordingly. |
| 74 | * |
| 75 | * Note: We may want to do something clever to ensure the framebuffer |
| 76 | * region is aligned such that we don't change dcache policy for other |
| 77 | * stuff inadvertantly. |
| 78 | * |
| 79 | * FIXME: Is disabling/re-enabling the MMU entirely necessary? |
| 80 | */ |
| 81 | uint32_t lower = ALIGN_DOWN(lcdbase, MiB); |
| 82 | uint32_t upper = ALIGN_UP(lcdbase + fb_size + 64*KiB, MiB); |
| 83 | dcache_clean_invalidate_by_mva(lower, upper - lower); |
| 84 | dcache_mmu_disable(); |
| 85 | mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); |
| 86 | dcache_mmu_enable(); |
| 87 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 88 | lcdbase += 64*KiB; |
Ronald G. Minnich | e8a9134 | 2013-04-22 10:46:53 -0700 | [diff] [blame] | 89 | mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 90 | printk(BIOS_DEBUG, |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 91 | "Initializing exynos VGA, base %p\n", (void *)lcdbase); |
| 92 | memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 93 | ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); |
| 94 | } |
| 95 | |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 96 | static void cpu_init(device_t dev) |
| 97 | { |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 98 | exynos_displayport_init(dev); |
David Hendricks | 3cc0d1e | 2013-03-26 16:28:21 -0700 | [diff] [blame] | 99 | ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | static void cpu_noop(device_t dev) |
| 103 | { |
| 104 | } |
| 105 | |
| 106 | static struct device_operations cpu_ops = { |
| 107 | .read_resources = cpu_noop, |
| 108 | .set_resources = cpu_noop, |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 109 | .enable_resources = cpu_init, |
| 110 | .init = cpu_noop, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 111 | .scan_bus = 0, |
| 112 | }; |
| 113 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 114 | static void enable_exynos5250_dev(device_t dev) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 115 | { |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 116 | dev->ops = &cpu_ops; |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | struct chip_operations cpu_samsung_exynos5250_ops = { |
| 120 | CHIP_NAME("CPU Samsung Exynos 5250") |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 121 | .enable_dev = enable_exynos5250_dev, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 122 | }; |
David Hendricks | c01d138 | 2013-03-28 19:04:58 -0700 | [diff] [blame] | 123 | |
| 124 | void exynos5250_config_l2_cache(void) |
| 125 | { |
| 126 | uint32_t val; |
| 127 | |
| 128 | /* |
| 129 | * Bit 9 - L2 tag RAM setup (1 cycle) |
| 130 | * Bits 8:6 - L2 tag RAM latency (3 cycles) |
| 131 | * Bit 5 - L2 data RAM setup (1 cycle) |
| 132 | * Bits 2:0 - L2 data RAM latency (3 cycles) |
| 133 | */ |
| 134 | val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); |
| 135 | write_l2ctlr(val); |
| 136 | } |