Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1 | #ifndef PC80_MC146818RTC_H |
| 2 | #define PC80_MC146818RTC_H |
| 3 | |
Edward O'Callaghan | c5fff75 | 2014-06-24 16:29:12 +1000 | [diff] [blame] | 4 | #if CONFIG_ARCH_X86 |
| 5 | |
Edward O'Callaghan | 502c3db | 2014-06-21 23:02:46 +1000 | [diff] [blame] | 6 | #include <arch/io.h> |
Alexandru Gagniuc | d7134e0 | 2013-11-23 18:54:44 -0600 | [diff] [blame] | 7 | #include <types.h> |
| 8 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 9 | #ifndef RTC_BASE_PORT |
| 10 | #define RTC_BASE_PORT 0x70 |
| 11 | #endif |
| 12 | |
| 13 | #define RTC_PORT(x) (RTC_BASE_PORT + (x)) |
| 14 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 15 | /* control registers - Moto names |
| 16 | */ |
| 17 | #define RTC_REG_A 10 |
| 18 | #define RTC_REG_B 11 |
| 19 | #define RTC_REG_C 12 |
| 20 | #define RTC_REG_D 13 |
| 21 | |
| 22 | |
| 23 | /********************************************************************** |
| 24 | * register details |
| 25 | **********************************************************************/ |
| 26 | #define RTC_FREQ_SELECT RTC_REG_A |
| 27 | |
| 28 | /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, |
| 29 | * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 30 | * totaling to a max high interval of 2.228 ms. |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 31 | */ |
| 32 | # define RTC_UIP 0x80 |
| 33 | # define RTC_DIV_CTL 0x70 |
| 34 | /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ |
| 35 | # define RTC_REF_CLCK_4MHZ 0x00 |
| 36 | # define RTC_REF_CLCK_1MHZ 0x10 |
| 37 | # define RTC_REF_CLCK_32KHZ 0x20 |
| 38 | /* 2 values for divider stage reset, others for "testing purposes only" */ |
| 39 | # define RTC_DIV_RESET1 0x60 |
| 40 | # define RTC_DIV_RESET2 0x70 |
| 41 | /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ |
| 42 | # define RTC_RATE_SELECT 0x0F |
| 43 | # define RTC_RATE_NONE 0x00 |
| 44 | # define RTC_RATE_32786HZ 0x01 |
| 45 | # define RTC_RATE_16384HZ 0x02 |
| 46 | # define RTC_RATE_8192HZ 0x03 |
| 47 | # define RTC_RATE_4096HZ 0x04 |
| 48 | # define RTC_RATE_2048HZ 0x05 |
| 49 | # define RTC_RATE_1024HZ 0x06 |
| 50 | # define RTC_RATE_512HZ 0x07 |
| 51 | # define RTC_RATE_256HZ 0x08 |
| 52 | # define RTC_RATE_128HZ 0x09 |
| 53 | # define RTC_RATE_64HZ 0x0a |
| 54 | # define RTC_RATE_32HZ 0x0b |
| 55 | # define RTC_RATE_16HZ 0x0c |
| 56 | # define RTC_RATE_8HZ 0x0d |
| 57 | # define RTC_RATE_4HZ 0x0e |
| 58 | # define RTC_RATE_2HZ 0x0f |
| 59 | |
| 60 | /**********************************************************************/ |
| 61 | #define RTC_CONTROL RTC_REG_B |
| 62 | # define RTC_SET 0x80 /* disable updates for clock setting */ |
| 63 | # define RTC_PIE 0x40 /* periodic interrupt enable */ |
| 64 | # define RTC_AIE 0x20 /* alarm interrupt enable */ |
| 65 | # define RTC_UIE 0x10 /* update-finished interrupt enable */ |
| 66 | # define RTC_SQWE 0x08 /* enable square-wave output */ |
| 67 | # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ |
| 68 | # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ |
| 69 | # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ |
| 70 | |
| 71 | /**********************************************************************/ |
| 72 | #define RTC_INTR_FLAGS RTC_REG_C |
| 73 | /* caution - cleared by read */ |
| 74 | # define RTC_IRQF 0x80 /* any of the following 3 is active */ |
| 75 | # define RTC_PF 0x40 |
| 76 | # define RTC_AF 0x20 |
| 77 | # define RTC_UF 0x10 |
| 78 | |
| 79 | /**********************************************************************/ |
| 80 | #define RTC_VALID RTC_REG_D |
| 81 | # define RTC_VRT 0x80 /* valid RAM and time */ |
| 82 | /**********************************************************************/ |
| 83 | |
Duncan Laurie | c8c836f | 2012-06-23 13:22:25 -0700 | [diff] [blame] | 84 | /* Date and Time in RTC CMOS */ |
| 85 | #define RTC_CLK_SECOND 0 |
| 86 | #define RTC_CLK_SECOND_ALARM 1 |
| 87 | #define RTC_CLK_MINUTE 2 |
| 88 | #define RTC_CLK_MINUTE_ALARM 3 |
| 89 | #define RTC_CLK_HOUR 4 |
| 90 | #define RTC_CLK_HOUR_ALARM 5 |
| 91 | #define RTC_CLK_DAYOFWEEK 6 |
| 92 | #define RTC_CLK_DAYOFMONTH 7 |
| 93 | #define RTC_CLK_MONTH 8 |
| 94 | #define RTC_CLK_YEAR 9 |
zbao | a1e6a9c | 2012-08-02 19:02:26 +0800 | [diff] [blame] | 95 | #define RTC_CLK_ALTCENTURY 0x32 |
| 96 | |
| 97 | #define RTC_HAS_ALTCENTURY 1 |
| 98 | #define RTC_HAS_NO_ALTCENTURY 0 |
Duncan Laurie | c8c836f | 2012-06-23 13:22:25 -0700 | [diff] [blame] | 99 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 100 | /* On PCs, the checksum is built only over bytes 16..45 */ |
| 101 | #define PC_CKS_RANGE_START 16 |
| 102 | #define PC_CKS_RANGE_END 45 |
| 103 | #define PC_CKS_LOC 46 |
| 104 | |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 105 | #ifndef UTIL_BUILD_OPTION_TABLE |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 106 | static inline unsigned char cmos_read(unsigned char addr) |
| 107 | { |
| 108 | int offs = 0; |
| 109 | if (addr >= 128) { |
| 110 | offs = 2; |
| 111 | addr -= 128; |
| 112 | } |
| 113 | outb(addr, RTC_BASE_PORT + offs + 0); |
| 114 | return inb(RTC_BASE_PORT + offs + 1); |
| 115 | } |
| 116 | |
Patrick Georgi | f943901 | 2012-11-15 14:54:05 +0100 | [diff] [blame] | 117 | static inline void cmos_write_inner(unsigned char val, unsigned char addr) |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 118 | { |
| 119 | int offs = 0; |
| 120 | if (addr >= 128) { |
| 121 | offs = 2; |
| 122 | addr -= 128; |
| 123 | } |
| 124 | outb(addr, RTC_BASE_PORT + offs + 0); |
| 125 | outb(val, RTC_BASE_PORT + offs + 1); |
| 126 | } |
Duncan Laurie | 654f293 | 2011-09-26 13:24:40 -0700 | [diff] [blame] | 127 | |
Patrick Georgi | f943901 | 2012-11-15 14:54:05 +0100 | [diff] [blame] | 128 | static inline void cmos_write(unsigned char val, unsigned char addr) |
| 129 | { |
| 130 | u8 control_state = cmos_read(RTC_CONTROL); |
| 131 | /* There are various places where RTC bits might be hiding, |
| 132 | * eg. the Century / AltCentury byte. So to be safe, disable |
| 133 | * RTC before changing any value. |
| 134 | */ |
| 135 | if ((addr != RTC_CONTROL) && !(control_state & RTC_SET)) { |
| 136 | cmos_write_inner(control_state | RTC_SET, RTC_CONTROL); |
| 137 | } |
| 138 | cmos_write_inner(val, addr); |
| 139 | /* reset to prior configuration */ |
| 140 | if ((addr != RTC_CONTROL) && !(control_state & RTC_SET)) { |
| 141 | cmos_write_inner(control_state, RTC_CONTROL); |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static inline void cmos_disable_rtc(void) |
| 146 | { |
| 147 | u8 control_state = cmos_read(RTC_CONTROL); |
| 148 | cmos_write(control_state | RTC_SET, RTC_CONTROL); |
| 149 | } |
| 150 | |
| 151 | static inline void cmos_enable_rtc(void) |
| 152 | { |
| 153 | u8 control_state = cmos_read(RTC_CONTROL); |
| 154 | cmos_write(control_state & ~RTC_SET, RTC_CONTROL); |
| 155 | } |
| 156 | |
Duncan Laurie | 654f293 | 2011-09-26 13:24:40 -0700 | [diff] [blame] | 157 | static inline u32 cmos_read32(u8 offset) |
| 158 | { |
| 159 | u32 value = 0; |
| 160 | u8 i; |
| 161 | for (i = 0; i < sizeof(value); ++i) |
| 162 | value |= cmos_read(offset + i) << (i << 3); |
| 163 | return value; |
| 164 | } |
| 165 | |
| 166 | static inline void cmos_write32(u8 offset, u32 value) |
| 167 | { |
| 168 | u8 i; |
| 169 | for (i = 0; i < sizeof(value); ++i) |
| 170 | cmos_write((value >> (i << 3)) & 0xff, offset + i); |
| 171 | } |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 172 | #endif |
| 173 | |
| 174 | #if !defined(__ROMCC__) |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 175 | void cmos_init(int invalid); |
| 176 | void cmos_check_update_date(u8 has_century); |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 177 | #if CONFIG_USE_OPTION_TABLE |
Alexandru Gagniuc | d7134e0 | 2013-11-23 18:54:44 -0600 | [diff] [blame] | 178 | enum cb_err set_option(const char *name, void *val); |
| 179 | enum cb_err get_option(void *dest, const char *name); |
Patrick Georgi | b251753 | 2011-05-10 21:53:13 +0000 | [diff] [blame] | 180 | unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 181 | #else |
Alexandru Gagniuc | d7134e0 | 2013-11-23 18:54:44 -0600 | [diff] [blame] | 182 | static inline enum cb_err set_option(const char *name __attribute__((unused)), |
| 183 | void *val __attribute__((unused))) |
| 184 | { return CB_CMOS_OTABLE_DISABLED; }; |
| 185 | static inline enum cb_err get_option(void *dest __attribute__((unused)), |
| 186 | const char *name __attribute__((unused))) |
| 187 | { return CB_CMOS_OTABLE_DISABLED; } |
Patrick Georgi | a27561c | 2011-11-22 10:27:24 +0100 | [diff] [blame] | 188 | #define read_option_lowlevel(start, size, def) def |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 189 | #endif |
Edward O'Callaghan | d638c2b | 2014-06-26 18:11:07 +1000 | [diff] [blame] | 190 | #else /* defined(__ROMCC__) */ |
Stefan Reinauer | ae5e11d | 2012-04-27 02:31:28 +0200 | [diff] [blame] | 191 | #include <drivers/pc80/mc146818rtc_early.c> |
Edward O'Callaghan | d638c2b | 2014-06-26 18:11:07 +1000 | [diff] [blame] | 192 | #endif /* !defined(__ROMCC__) */ |
Patrick Georgi | b251753 | 2011-05-10 21:53:13 +0000 | [diff] [blame] | 193 | #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default)) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 194 | |
Duncan Laurie | b6e97b1 | 2012-09-09 19:09:56 -0700 | [diff] [blame] | 195 | #if CONFIG_CMOS_POST |
| 196 | #if CONFIG_USE_OPTION_TABLE |
| 197 | # include "option_table.h" |
| 198 | # define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) |
| 199 | #else |
| 200 | # if defined(CONFIG_CMOS_POST_OFFSET) |
| 201 | # define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET |
| 202 | # else |
| 203 | # error "Must define CONFIG_CMOS_POST_OFFSET" |
| 204 | # endif |
| 205 | #endif |
| 206 | |
Duncan Laurie | d5686fe | 2013-06-10 10:21:41 -0700 | [diff] [blame] | 207 | /* |
| 208 | * 0 = Bank Select Magic |
| 209 | * 1 = Bank 0 POST |
| 210 | * 2 = Bank 1 POST |
| 211 | * 3-6 = BANK 0 Extra log |
| 212 | * 7-10 = BANK 1 Extra log |
| 213 | */ |
Duncan Laurie | b6e97b1 | 2012-09-09 19:09:56 -0700 | [diff] [blame] | 214 | #define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET) |
| 215 | #define CMOS_POST_BANK_0_MAGIC 0x80 |
| 216 | #define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1) |
Duncan Laurie | d5686fe | 2013-06-10 10:21:41 -0700 | [diff] [blame] | 217 | #define CMOS_POST_BANK_0_EXTRA (CMOS_POST_OFFSET + 3) |
Duncan Laurie | b6e97b1 | 2012-09-09 19:09:56 -0700 | [diff] [blame] | 218 | #define CMOS_POST_BANK_1_MAGIC 0x81 |
| 219 | #define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) |
Duncan Laurie | d5686fe | 2013-06-10 10:21:41 -0700 | [diff] [blame] | 220 | #define CMOS_POST_BANK_1_EXTRA (CMOS_POST_OFFSET + 7) |
Duncan Laurie | 1fc3461 | 2012-09-09 19:14:45 -0700 | [diff] [blame] | 221 | |
Duncan Laurie | 8adf7a2 | 2013-06-10 10:34:20 -0700 | [diff] [blame] | 222 | #define CMOS_POST_EXTRA_DEV_PATH 0x01 |
| 223 | |
Duncan Laurie | 1fc3461 | 2012-09-09 19:14:45 -0700 | [diff] [blame] | 224 | void cmos_post_log(void); |
Edward O'Callaghan | 5c97142 | 2014-04-15 14:32:53 +1000 | [diff] [blame] | 225 | #else |
| 226 | static inline void cmos_post_log(void) {} |
Duncan Laurie | b6e97b1 | 2012-09-09 19:09:56 -0700 | [diff] [blame] | 227 | #endif /* CONFIG_CMOS_POST */ |
| 228 | |
Edward O'Callaghan | c5fff75 | 2014-06-24 16:29:12 +1000 | [diff] [blame] | 229 | #endif /* CONFIG_ARCH_X86 */ |
| 230 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 231 | #endif /* PC80_MC146818RTC_H */ |