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Angel Pons585495e2020-04-03 01:21:38 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Gerd Hoffmannee941b382013-06-07 16:03:44 +02002
Kyösti Mälkkia963acd2019-08-16 20:34:25 +03003#include <arch/romstage.h>
Patrick Rudolph69d5ef92018-11-11 12:43:48 +01004#include <cbmem.h>
Patrick Rudolph1af89232018-11-11 12:50:51 +01005#include <southbridge/intel/i82801ix/i82801ix.h>
Patrick Rudolphfbdeb4a2019-02-14 19:47:03 +01006#include <device/pci_ops.h>
7
Angel Pons899525d2021-01-28 10:57:13 +01008#include "q35.h"
Patrick Rudolphfbdeb4a2019-02-14 19:47:03 +01009
Patrick Rudolph0395b4b2024-06-14 17:07:29 +020010#define TSEG_SZ_MASK (3 << 1)
11
Kyösti Mälkkif0a3d442019-08-18 08:02:23 +030012void mainboard_romstage_entry(void)
Gerd Hoffmannee941b382013-06-07 16:03:44 +020013{
Gerd Hoffmannee941b382013-06-07 16:03:44 +020014 i82801ix_early_init();
Gerd Hoffmannee941b382013-06-07 16:03:44 +020015
Angel Ponscba669c2021-01-28 11:56:45 +010016 if (!CONFIG(BOOTBLOCK_CONSOLE))
17 mainboard_machine_check();
Patrick Rudolphfbdeb4a2019-02-14 19:47:03 +010018
Patrick Rudolph0395b4b2024-06-14 17:07:29 +020019 /* Configure requested TSEG size */
20 switch (CONFIG_SMM_TSEG_SIZE) {
21 case 1 * MiB:
22 pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 0 << 1);
23 break;
24 case 2 * MiB:
25 pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 1 << 1);
26 break;
27 case 8 * MiB:
28 pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 2 << 1);
29 break;
30 default:
31 printk(BIOS_WARNING, "%s: Unsupported TSEG size: 0x%x\n", __func__, CONFIG_SMM_TSEG_SIZE);
32 }
33
Patrick Rudolph1af89232018-11-11 12:50:51 +010034 cbmem_recovery(0);
Gerd Hoffmannee941b382013-06-07 16:03:44 +020035}