Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <delay.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 27 | #include <soc/iobp.h> |
| 28 | #include <soc/ramstage.h> |
| 29 | #include <soc/rcba.h> |
| 30 | #include <soc/sata.h> |
| 31 | #include <soc/intel/broadwell/chip.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 32 | |
| 33 | static inline u32 sir_read(struct device *dev, int idx) |
| 34 | { |
| 35 | pci_write_config32(dev, SATA_SIRI, idx); |
| 36 | return pci_read_config32(dev, SATA_SIRD); |
| 37 | } |
| 38 | |
| 39 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 40 | { |
| 41 | pci_write_config32(dev, SATA_SIRI, idx); |
| 42 | pci_write_config32(dev, SATA_SIRD, value); |
| 43 | } |
| 44 | |
| 45 | static void sata_init(struct device *dev) |
| 46 | { |
| 47 | config_t *config = dev->chip_info; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 48 | u32 reg32; |
| 49 | u8 *abar; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 50 | u16 reg16; |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 51 | int port; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 52 | |
| 53 | printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); |
| 54 | |
| 55 | /* Enable BARs */ |
| 56 | pci_write_config16(dev, PCI_COMMAND, 0x0007); |
| 57 | |
| 58 | /* Set Interrupt Line */ |
| 59 | /* Interrupt Pin is set by D31IP.PIP */ |
| 60 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); |
| 61 | |
| 62 | /* Set timings */ |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 63 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); |
| 64 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 65 | |
| 66 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 67 | reg16 = pci_read_config16(dev, 0x92); |
| 68 | reg16 &= ~0x3f; |
| 69 | reg16 |= 0x8000 | config->sata_port_map; |
| 70 | pci_write_config16(dev, 0x92, reg16); |
| 71 | udelay(2); |
| 72 | |
| 73 | /* Setup register 98h */ |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 74 | reg32 = pci_read_config32(dev, 0x98); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 75 | reg32 &= ~((1 << 31) | (1 << 30)); |
| 76 | reg32 |= 1 << 23; |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 77 | reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 78 | pci_write_config32(dev, 0x98, reg32); |
| 79 | |
| 80 | /* Setup register 9Ch */ |
| 81 | reg16 = 0; /* Disable alternate ID */ |
| 82 | reg16 = 1 << 5; /* BWG step 12 */ |
| 83 | pci_write_config16(dev, 0x9c, reg16); |
| 84 | |
| 85 | /* SATA Initialization register */ |
| 86 | reg32 = 0x183; |
| 87 | reg32 |= (config->sata_port_map ^ 0x3f) << 24; |
| 88 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 89 | pci_write_config32(dev, 0x94, reg32); |
| 90 | |
| 91 | /* Initialize AHCI memory-mapped space */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 92 | abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5)); |
| 93 | printk(BIOS_DEBUG, "ABAR: %p\n", abar); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 94 | |
Duncan Laurie | 55228ba | 2014-08-25 10:14:08 -0700 | [diff] [blame] | 95 | /* CAP (HBA Capabilities) : enable power management */ |
| 96 | reg32 = read32(abar + 0x00); |
| 97 | reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ |
| 98 | reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ |
| 99 | reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */ |
| 100 | write32(abar + 0x00, reg32); |
| 101 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 102 | /* PI (Ports implemented) */ |
| 103 | write32(abar + 0x0c, config->sata_port_map); |
| 104 | (void) read32(abar + 0x0c); /* Read back 1 */ |
| 105 | (void) read32(abar + 0x0c); /* Read back 2 */ |
| 106 | |
| 107 | /* CAP2 (HBA Capabilities Extended)*/ |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 108 | if (config->sata_devslp_disable) { |
| 109 | reg32 = read32(abar + 0x24); |
| 110 | reg32 &= ~(1 << 3); |
| 111 | write32(abar + 0x24, reg32); |
| 112 | } else { |
| 113 | /* Enable DEVSLP */ |
| 114 | reg32 = read32(abar + 0x24); |
| 115 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 116 | write32(abar + 0x24, reg32); |
| 117 | |
| 118 | for (port = 0; port < 4; port++) { |
| 119 | if (!(config->sata_port_map & (1 << port))) |
| 120 | continue; |
| 121 | reg32 = read32(abar + 0x144 + (0x80 * port)); |
| 122 | reg32 |= (1 << 1); /* DEVSLP DSP */ |
| 123 | write32(abar + 0x144 + (0x80 * port), reg32); |
| 124 | } |
| 125 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 126 | |
| 127 | /* |
| 128 | * Static Power Gating for unused ports |
| 129 | */ |
| 130 | reg32 = RCBA32(0x3a84); |
| 131 | /* Port 3 and 2 disabled */ |
| 132 | if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) |
| 133 | reg32 |= (1 << 24) | (1 << 26); |
| 134 | /* Port 1 and 0 disabled */ |
| 135 | if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) |
| 136 | reg32 |= (1 << 20) | (1 << 18); |
| 137 | RCBA32(0x3a84) = reg32; |
| 138 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 139 | /* Set Gen3 Transmitter settings if needed */ |
| 140 | if (config->sata_port0_gen3_tx) |
Duncan Laurie | b63d341 | 2015-01-06 13:32:42 -0800 | [diff] [blame] | 141 | pch_iobp_update(SATA_IOBP_SP0_SECRT88, |
| 142 | ~(SATA_SECRT88_VADJ_MASK << |
| 143 | SATA_SECRT88_VADJ_SHIFT), |
| 144 | (config->sata_port0_gen3_tx & |
| 145 | SATA_SECRT88_VADJ_MASK) |
| 146 | << SATA_SECRT88_VADJ_SHIFT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 147 | |
| 148 | if (config->sata_port1_gen3_tx) |
Duncan Laurie | b63d341 | 2015-01-06 13:32:42 -0800 | [diff] [blame] | 149 | pch_iobp_update(SATA_IOBP_SP1_SECRT88, |
| 150 | ~(SATA_SECRT88_VADJ_MASK << |
| 151 | SATA_SECRT88_VADJ_SHIFT), |
| 152 | (config->sata_port1_gen3_tx & |
| 153 | SATA_SECRT88_VADJ_MASK) |
| 154 | << SATA_SECRT88_VADJ_SHIFT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 155 | |
| 156 | /* Set Gen3 DTLE DATA / EDGE registers if needed */ |
| 157 | if (config->sata_port0_gen3_dtle) { |
| 158 | pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, |
| 159 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 160 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 161 | << SATA_DTLE_DATA_SHIFT); |
| 162 | |
| 163 | pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, |
| 164 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 165 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 166 | << SATA_DTLE_EDGE_SHIFT); |
| 167 | } |
| 168 | |
| 169 | if (config->sata_port1_gen3_dtle) { |
| 170 | pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, |
| 171 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 172 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 173 | << SATA_DTLE_DATA_SHIFT); |
| 174 | |
| 175 | pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, |
| 176 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 177 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 178 | << SATA_DTLE_EDGE_SHIFT); |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * Additional Programming Requirements for Power Optimizer |
| 183 | */ |
| 184 | |
| 185 | /* Step 1 */ |
| 186 | sir_write(dev, 0x64, 0x883c9003); |
| 187 | |
| 188 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
| 189 | reg32 = sir_read(dev, 0x68); |
| 190 | reg32 &= 0xffff0000; |
| 191 | reg32 |= 0x880a; |
| 192 | sir_write(dev, 0x68, reg32); |
| 193 | |
| 194 | /* Step 3: SIR 60h[3] = 1 */ |
| 195 | reg32 = sir_read(dev, 0x60); |
| 196 | reg32 |= (1 << 3); |
| 197 | sir_write(dev, 0x60, reg32); |
| 198 | |
| 199 | /* Step 4: SIR 60h[0] = 1 */ |
| 200 | reg32 = sir_read(dev, 0x60); |
| 201 | reg32 |= (1 << 0); |
| 202 | sir_write(dev, 0x60, reg32); |
| 203 | |
| 204 | /* Step 5: SIR 60h[1] = 1 */ |
| 205 | reg32 = sir_read(dev, 0x60); |
| 206 | reg32 |= (1 << 1); |
| 207 | sir_write(dev, 0x60, reg32); |
| 208 | |
| 209 | /* Clock Gating */ |
| 210 | sir_write(dev, 0x70, 0x3f00bf1f); |
| 211 | sir_write(dev, 0x54, 0xcf000f0f); |
| 212 | sir_write(dev, 0x58, 0x00190000); |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 213 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 214 | |
| 215 | reg32 = pci_read_config32(dev, 0x300); |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 216 | reg32 |= (1 << 17) | (1 << 16) | (1 << 19); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 217 | reg32 |= (1 << 31) | (1 << 30) | (1 << 29); |
| 218 | pci_write_config32(dev, 0x300, reg32); |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 219 | |
Kane Chen | 4613472 | 2014-08-28 17:05:06 -0700 | [diff] [blame] | 220 | reg32 = pci_read_config32(dev, 0x98); |
| 221 | reg32 |= 1 << 29; |
| 222 | pci_write_config32(dev, 0x98, reg32); |
| 223 | |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 224 | /* Register Lock */ |
| 225 | reg32 = pci_read_config32(dev, 0x9c); |
| 226 | reg32 |= (1 << 31); |
| 227 | pci_write_config32(dev, 0x9c, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | /* |
| 231 | * Set SATA controller mode early so the resource allocator can |
| 232 | * properly assign IO/Memory resources for the controller. |
| 233 | */ |
| 234 | static void sata_enable(device_t dev) |
| 235 | { |
| 236 | /* Get the chip configuration */ |
| 237 | config_t *config = dev->chip_info; |
| 238 | u16 map = 0x0060; |
| 239 | |
| 240 | map |= (config->sata_port_map ^ 0x3f) << 8; |
| 241 | |
| 242 | pci_write_config16(dev, 0x90, map); |
| 243 | } |
| 244 | |
| 245 | static struct device_operations sata_ops = { |
| 246 | .read_resources = &pci_dev_read_resources, |
| 247 | .set_resources = &pci_dev_set_resources, |
| 248 | .enable_resources = &pci_dev_enable_resources, |
| 249 | .init = &sata_init, |
| 250 | .enable = &sata_enable, |
| 251 | .ops_pci = &broadwell_pci_ops, |
| 252 | }; |
| 253 | |
| 254 | static const unsigned short pci_device_ids[] = { |
| 255 | 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* LynxPoint-LP */ |
| 256 | 0x9c83, 0x9c85, 0x282a, 0x9c87, 0x282a, 0x9c8f, /* WildcatPoint */ |
| 257 | 0 |
| 258 | }; |
| 259 | |
| 260 | static const struct pci_driver pch_sata __pci_driver = { |
| 261 | .ops = &sata_ops, |
| 262 | .vendor = PCI_VENDOR_ID_INTEL, |
| 263 | .devices = pci_device_ids, |
| 264 | }; |