Uwe Hermann | c70e9fc | 2010-02-15 23:10:19 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007-2009 coresystems GmbH |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Uwe Hermann | c70e9fc | 2010-02-15 23:10:19 +0000 | [diff] [blame] | 18 | ## |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 19 | |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 20 | config NORTHBRIDGE_INTEL_I945 |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 21 | bool |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 22 | |
| 23 | if NORTHBRIDGE_INTEL_I945 |
| 24 | |
| 25 | config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy |
| 26 | def_bool y |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 27 | select HAVE_DEBUG_RAM_SETUP |
Denis 'GNUtoo' Carikli | fd39ddd | 2013-06-04 04:48:11 +0200 | [diff] [blame] | 28 | select LAPIC_MONOTONIC_TIMER |
Uwe Hermann | 81b3c0a | 2009-10-30 12:56:59 +0000 | [diff] [blame] | 29 | |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 30 | config NORTHBRIDGE_INTEL_SUBTYPE_I945GC |
| 31 | def_bool n |
| 32 | config NORTHBRIDGE_INTEL_SUBTYPE_I945GM |
| 33 | def_bool n |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 34 | |
Stefan Reinauer | bccbbe6 | 2010-12-19 21:20:14 +0000 | [diff] [blame] | 35 | config VGA_BIOS_ID |
Uwe Hermann | 81b3c0a | 2009-10-30 12:56:59 +0000 | [diff] [blame] | 36 | string |
| 37 | default "8086,27a2" |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 38 | |
| 39 | config CHANNEL_XOR_RANDOMIZATION |
| 40 | bool |
| 41 | default n |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 42 | |
| 43 | config OVERRIDE_CLOCK_DISABLE |
| 44 | bool |
| 45 | default n |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 46 | help |
| 47 | Usually system firmware turns off system memory clock |
| 48 | signals to unused SO-DIMM slots to reduce EMI and power |
| 49 | consumption. |
| 50 | However, some boards do not like unused clock signals to |
| 51 | be disabled. |
| 52 | |
| 53 | config MAXIMUM_SUPPORTED_FREQUENCY |
| 54 | int |
| 55 | default 0 |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 56 | help |
| 57 | If non-zero, this designates the maximum DDR frequency |
| 58 | the board supports, despite what the chipset should be |
| 59 | capable of. |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 60 | |
Peter Stuge | 751508a | 2012-01-27 22:17:09 +0100 | [diff] [blame] | 61 | config CHECK_SLFRCS_ON_RESUME |
| 62 | def_bool n |
| 63 | help |
| 64 | On some boards it may be neccessary to hard reset early |
| 65 | during resume from S3 if the SLFRCS register indicates that |
| 66 | a memory channel is not guaranteed to be in self-refresh. |
| 67 | On other boards the check always creates a false positive, |
| 68 | effectively making it impossible to resume. |
| 69 | |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 70 | endif |