Blame - src/mainboard/pcengines/apu2/Kconfig - coreboot

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Patrick Georgi	c49d7a3	2020-05-08 22:50:46 +0200	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	2
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	3	if BOARD_PCENGINES_APU2 \|\| BOARD_PCENGINES_APU3 \|\| BOARD_PCENGINES_APU4 \|\| \
				4	BOARD_PCENGINES_APU5
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	5
Elyes HAOUAS	f0c5be2	2018-11-27 20:36:44 +0100	[diff] [blame]	6	config BOARD_SPECIFIC_OPTIONS
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	7	def_bool y
				8	select CPU_AMD_PI_00730F01
				9	select NORTHBRIDGE_AMD_PI_00730F01
				10	select SOUTHBRIDGE_AMD_PI_AVALON
Kyösti Mälkki	657d68b	2019-12-03 12:36:09 +0200	[diff] [blame]	11	select DEFAULT_POST_ON_LPC
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	12	select SUPERIO_NUVOTON_NCT5104D
				13	select HAVE_PIRQ_TABLE
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	14	select HAVE_ACPI_TABLES
				15	select BOARD_ROMSIZE_KB_8192
Michael Niewöhner	87cc889	2020-09-07 14:26:09 +0200	[diff] [blame]	16	select HAVE_SPD_IN_CBFS
Jes B. Klinke	c6b041a1	2022-04-19 14:00:33 -0700	[diff] [blame]	17	select MEMORY_MAPPED_TPM
Michał Żygowski	54fcb78	2018-08-03 18:23:52 +0200	[diff] [blame]	18	select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
Michał Żygowski	8e46d42	2020-03-20 16:19:55 +0100	[diff] [blame]	19	select PCIEXP_ASPM
				20	select PCIEXP_CLK_PM
				21	select PCIEXP_COMMON_CLOCK
				22	select PCIEXP_L1_SUB_STATE
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	23
				24	config MAINBOARD_DIR
Patrick Georgi	0bb8346	2019-11-22 20:58:58 +0100	[diff] [blame]	25	default "pcengines/apu2"
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	26
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	27	config VARIANT_DIR
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	28	default "apu2" if BOARD_PCENGINES_APU2
				29	default "apu3" if BOARD_PCENGINES_APU3
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	30	default "apu4" if BOARD_PCENGINES_APU4
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	31	default "apu5" if BOARD_PCENGINES_APU5
				32
				33	config DEVICETREE
Patrick Georgi	b8fba86	2020-06-17 21:06:53 +0200	[diff] [blame]	34	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	35
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	36	config MAINBOARD_PART_NUMBER
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	37	default "apu2" if BOARD_PCENGINES_APU2
				38	default "apu3" if BOARD_PCENGINES_APU3
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	39	default "apu4" if BOARD_PCENGINES_APU4
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	40	default "apu5" if BOARD_PCENGINES_APU5
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	41
				42	config MAX_CPUS
				43	int
				44	default 4
				45
				46	config IRQ_SLOT_COUNT
				47	int
				48	default 11
				49
				50	config ONBOARD_VGA_IS_PRIMARY
				51	bool
				52	default y
				53
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	54	config AGESA_BINARY_PI_FILE
				55	string
				56	default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
				57
				58	choice
				59	prompt "J19 pins 1-10"
Michał Żygowski	cc16ec1	2018-09-24 13:17:40 +0200	[diff] [blame]	60	default APU2_PINMUX_UART_C
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	61
				62	config APU2_PINMUX_OFF_C
				63	bool "disable"
				64
				65	config APU2_PINMUX_GPIO0
				66	bool "GPIO"
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	67	depends on BOARD_PCENGINES_APU2 \|\| BOARD_PCENGINES_APU3 \|\| \
				68	BOARD_PCENGINES_APU4
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	69
				70	config APU2_PINMUX_UART_C
				71	bool "UART 0x3e8"
				72
				73	endchoice
				74
				75	choice
				76	prompt "J19 pins 11-20"
Michał Żygowski	cc16ec1	2018-09-24 13:17:40 +0200	[diff] [blame]	77	default APU2_PINMUX_UART_D
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	78
				79	config APU2_PINMUX_OFF_D
				80	bool "disable"
				81
				82	config APU2_PINMUX_GPIO1
				83	bool "GPIO"
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	84	depends on BOARD_PCENGINES_APU2 \|\| BOARD_PCENGINES_APU3 \|\| \
				85	BOARD_PCENGINES_APU4
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	86
				87	config APU2_PINMUX_UART_D
				88	bool "UART 0x2e8"
				89
				90	endchoice
				91
Patrick Georgi	44a46a1	2017-01-28 13:12:09 +0100	[diff] [blame]	92	config DIMM_SPD_SIZE
Patrick Georgi	44a46a1	2017-01-28 13:12:09 +0100	[diff] [blame]	93	default 128
				94
Piotr Kleinschmidt	7354605	2019-10-09 11:47:03 +0200	[diff] [blame]	95	config AGESA_USE_1_0_0_4_HEADER
				96	bool
				97	default y
				98	help
				99	Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is
				100	impossible to use the newest blob. Using an older 1.0.0.4 blob
				101	workarounds the problem, however some headers changes between blob
				102	revisions. This option removes the changes in headers introduced
				103	with AGESA 1.0.0.A to fit the 1.0.0.4 revision.
				104
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	105	endif # BOARD_PCENGINES_APU2