Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of msrtool. |
| 3 | * |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 4 | * Copyright (C) 2013 Anton Kochkov <anton.kochkov@gmail.com> |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include "msrtool.h" |
| 21 | |
Anton Kochkov | 59b36f1 | 2012-07-21 07:29:48 +0400 | [diff] [blame] | 22 | int intel_core2_later_probe(const struct targetdef *target, const struct cpuid_t *id) { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 23 | return ((0x6 == id->family)&(0x17 == id->model)); |
| 24 | } |
| 25 | |
| 26 | const struct msrdef intel_core2_later_msrs[] = { |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 27 | {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", |
| 28 | "Model Specific Platform ID", { |
| 29 | /* The OS can use this MSR to determine "slot" information for the |
| 30 | * processor and the proper microcode update to load. */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 31 | { 63, 11, RESERVED }, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 32 | { 52, 3, "Platform ID", "R/O", PRESENT_BIN, { |
| 33 | { MSR1(0), "Processor Flag 0" }, |
| 34 | { MSR1(1), "Processor Flag 1" }, |
| 35 | { MSR1(2), "Processor Flag 2" }, |
| 36 | { MSR1(3), "Processor Flag 3" }, |
| 37 | { MSR1(4), "Processor Flag 4" }, |
| 38 | { MSR1(5), "Processor Flag 5" }, |
| 39 | { MSR1(6), "Processor Flag 6" }, |
| 40 | { MSR1(7), "Processor Flag 7" }, |
| 41 | { BITVAL_EOT } |
| 42 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 43 | { 49, 37, RESERVED }, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 44 | { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio", |
| 45 | PRESENT_DEC, { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 46 | { BITVAL_EOT } |
| 47 | }}, |
| 48 | { 7, 8, RESERVED }, |
| 49 | { BITS_EOT } |
| 50 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 51 | { 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register", |
| 52 | "Processor Hard Power-On Configuration", { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 53 | { 63, 41, RESERVED }, |
| 54 | { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, { |
| 55 | { BITVAL_EOT } |
| 56 | }}, |
| 57 | { 21, 2, "Symmetric Arbitration ID:", "R/O", PRESENT_BIN, { |
| 58 | { BITVAL_EOT } |
| 59 | }}, |
| 60 | { 19, 1, RESERVED }, |
| 61 | { 18, 1, "N/2:", "Non-integer bus ratio", PRESENT_DEC, { |
| 62 | { MSR1(0), "Integer ratio" }, |
| 63 | { MSR1(1), "Non-integer ratio" }, |
| 64 | { BITVAL_EOT } |
| 65 | }}, |
| 66 | { 17, 2, "APIC Cluster ID:", "R/O", PRESENT_HEX, { |
| 67 | { BITVAL_EOT } |
| 68 | }}, |
| 69 | { 15, 1, RESERVED }, |
| 70 | { 14, 1, "1 Mbyte Power on Reset Vector", "R/O", PRESENT_DEC, { |
| 71 | { MSR1(0), "4 GBytes Power on Reset Vector" }, |
| 72 | { MSR1(1), "1 Mbyte Power on Reset Vector" }, |
| 73 | { BITVAL_EOT } |
| 74 | }}, |
| 75 | { 13, 1, RESERVED }, |
| 76 | { 12, 1, "BINIT# Observation", "R/O", PRESENT_DEC, { |
| 77 | { MSR1(0), "BINIT# Observation disabled" }, |
| 78 | { MSR1(1), "BINIT# Observation enabled" }, |
| 79 | { BITVAL_EOT } |
| 80 | }}, |
| 81 | { 11, 1, "TXT", "Intel TXT Capable Chipset", PRESENT_DEC, { |
| 82 | { MSR1(0), "Intel TXT Capable Chipset not present" }, |
| 83 | { MSR1(1), "Intel TXT Capable Chipset present" }, |
| 84 | { BITVAL_EOT } |
| 85 | }}, |
| 86 | { 10, 1, "MCERR# Observation:", "R/O", PRESENT_DEC, { |
| 87 | { MSR1(0), "MCERR# Observation disabled" }, |
| 88 | { MSR1(1), "MCERR# Observation enabled" }, |
| 89 | { BITVAL_EOT } |
| 90 | }}, |
| 91 | { 9, 1, "Execute BIST", "R/O", PRESENT_DEC, { |
| 92 | { MSR1(0), "Execute BIST disabled" }, |
| 93 | { MSR1(1), "Execute BIST enabled" }, |
| 94 | { BITVAL_EOT } |
| 95 | }}, |
| 96 | { 8, 1, "Output Tri-state", "R/O", PRESENT_DEC, { |
| 97 | { MSR1(0), "Output Tri-state disabled" }, |
| 98 | { MSR1(1), "Output Tri-state enabled" }, |
| 99 | { BITVAL_EOT } |
| 100 | }}, |
| 101 | { 7, 1, "BINIT# Driver Enable", "R/W", PRESENT_DEC, { |
| 102 | { MSR1(0), "BINIT# Driver disabled" }, |
| 103 | { MSR1(1), "BINIT# Driver enabled" }, |
| 104 | { BITVAL_EOT } |
| 105 | }}, |
| 106 | { 6, 2, RESERVED }, |
| 107 | { 4, 1, "Address parity enable", "R/W", PRESENT_DEC, { |
| 108 | { MSR1(0), "Address parity disabled" }, |
| 109 | { MSR1(1), "Address parity enabled" }, |
| 110 | { BITVAL_EOT } |
| 111 | }}, |
| 112 | { 3, 1, "MCERR# Driver Enable", "R/W", PRESENT_DEC, { |
| 113 | { MSR1(0), "MCERR# Driver disabled" }, |
| 114 | { MSR1(1), "MCERR# Driver enabled" }, |
| 115 | { BITVAL_EOT } |
| 116 | }}, |
| 117 | { 2, 1, "Response error checking enable", "R/W", PRESENT_DEC, { |
| 118 | { MSR1(0), "Response Error Checking disabled" }, |
| 119 | { MSR1(1), "Response Error Checking enabled" }, |
| 120 | { BITVAL_EOT } |
| 121 | }}, |
| 122 | { 1, 1, "Data error checking enable", "R/W", PRESENT_DEC, { |
| 123 | { MSR1(0), "Data error checking disabled" }, |
| 124 | { MSR1(1), "Data error checking enabled" }, |
| 125 | { BITVAL_EOT } |
| 126 | }}, |
| 127 | { 0, 1, RESERVED }, |
| 128 | { BITS_EOT } |
| 129 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 130 | {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { |
| 131 | /* This field indicates the intended scaleable bus clock speed */ |
| 132 | { 63, 61, RESERVED }, |
| 133 | { 2, 3, "Speed", "R/O", PRESENT_BIN, { |
| 134 | { MSR1(0), "267 MHz (FSB 1067)" }, |
| 135 | { MSR1(1), "133 MHz (FSB 533)" }, |
| 136 | { MSR1(2), "200 MHz (FSB 800)" }, |
| 137 | { MSR1(3), "167 MHz (FSB 667)" }, |
| 138 | { MSR1(4), "333 MHz (FSB 1333)" }, |
| 139 | { MSR1(5), "100 MHz (FSB 400)" }, |
| 140 | { MSR1(6), "400 MHz (FSB 1600)" }, |
| 141 | { BITVAL_EOT } |
| 142 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 143 | { BITS_EOT } |
| 144 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 145 | {0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { |
| 146 | { 63, 40, RESERVED }, |
| 147 | { 23, 1, "L2 Present", "R/O", PRESENT_BIN, { |
| 148 | { MSR1(0), "L2 Present" }, |
| 149 | { MSR1(1), "L2 Not Present" }, |
| 150 | { BITVAL_EOT } |
| 151 | }}, |
| 152 | { 22, 14, RESERVED }, |
| 153 | { 8, 1, "L2 Enabled", "R/W", PRESENT_BIN, { |
| 154 | /* Until this bit is set the processor will not respond |
| 155 | * to the WBINVD instruction or the assertion |
| 156 | * of the FLUSH# input. */ |
| 157 | { MSR1(0), "L2 is disabled" }, |
| 158 | { MSR1(1), "L2 cache has been initialized" }, |
| 159 | { BITVAL_EOT } |
| 160 | }}, |
| 161 | { 7, 7, RESERVED}, |
| 162 | { 0, 1, "L2 Hardware Enabled", "R/O", PRESENT_BIN, { |
| 163 | { MSR1(0), "L2 is hardware-disabled" }, |
| 164 | { MSR1(1), "L2 is hardware-enabled" }, |
| 165 | { BITVAL_EOT } |
| 166 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 167 | { BITS_EOT } |
| 168 | }}, |
| 169 | {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { |
| 170 | { BITS_EOT } |
| 171 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 172 | |
| 173 | // Per core msrs |
| 174 | |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 175 | {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ |
| 176 | Machine-Check Exception Address", { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 177 | { BITS_EOT } |
| 178 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 179 | {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ |
| 180 | Machine-Check Exception Type", { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 181 | { BITS_EOT } |
| 182 | }}, |
| 183 | {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { |
| 184 | { BITS_EOT } |
| 185 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 186 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 187 | { BITS_EOT } |
| 188 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 189 | {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", { |
| 190 | /* In Intel's manual there is MAXPHYWID, |
| 191 | * which determine index of highest bit of |
| 192 | * APIC Base itself, so marking it as |
| 193 | * 'RESERVED'. |
| 194 | */ |
| 195 | { 63, 52, RESERVED }, |
| 196 | { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN, { |
| 197 | { BITVAL_EOT } |
| 198 | }}, |
| 199 | { 10, 1, RESERVED }, |
| 200 | { 9, 1, RESERVED }, |
| 201 | { 8, 1, "BSP Flag", "R/W", PRESENT_BIN, { |
| 202 | { BITVAL_EOT } |
| 203 | }}, |
| 204 | { 7, 8, RESERVED }, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 205 | { BITS_EOT } |
| 206 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 207 | {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", |
| 208 | "Control features in Intel 64Processor", { |
| 209 | { 63, 48, RESERVED }, |
| 210 | /* if CPUID.01H: ECX[6] = 1 */ |
| 211 | { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, { |
| 212 | { MSR1(0), "SENTER leaf functions are disabled" }, |
| 213 | { MSR1(1), "SENTER leaf functions are enabled" }, |
| 214 | { BITVAL_EOT } |
| 215 | }}, |
| 216 | /* if CPUID.01H: ECX[6] = 1 */ |
| 217 | { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, { |
| 218 | { BITVAL_EOT } |
| 219 | }}, |
| 220 | { 7, 4, RESERVED }, |
| 221 | { 3, 1, "SMRR Enable", "R/WL", PRESENT_BIN, { |
| 222 | { MSR1(0), "SMRR_PHYS_BASE and SMRR_PHYS_MASK are invisible in SMM" }, |
| 223 | { MSR1(1), "SMRR_PHYS_BASE and SMRR_PHYS_MASK accessible from SMM" }, |
| 224 | { BITVAL_EOT } |
| 225 | }}, |
| 226 | /* if CPUID.01H: ECX[5 or 6] = 1 */ |
| 227 | { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, { |
| 228 | /* This bit enables VMX for system executive |
| 229 | * that do not require SMX. |
| 230 | */ |
| 231 | { MSR1(0), "VMX outside of SMX operation disabled" }, |
| 232 | { MSR1(1), "VMX outside of SMX operation enabled" }, |
| 233 | { BITVAL_EOT } |
| 234 | }}, |
| 235 | { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { |
| 236 | /* This bit enables a system executive to use |
| 237 | * VMX in conjuction with SMX to support Intel |
| 238 | * Trusted Execution Technology. |
| 239 | */ |
| 240 | { MSR1(0), "VMX inside of SMX operation disabled" }, |
| 241 | { MSR1(1), "VMX outside of SMX operation enabled" }, |
| 242 | { BITVAL_EOT } |
| 243 | }}, |
| 244 | /* if CPUID.01H: ECX[5 or 6] = 1 */ |
| 245 | { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, { |
| 246 | /* Once the Lock bit is set, the contents |
| 247 | * of this register cannot be modified. |
| 248 | * Therefore the lock bit must be set after |
| 249 | * configuring support for Intel Virtualization |
| 250 | * Technology and prior transferring control |
| 251 | * to an Option ROM or bootloader. Hence, once |
| 252 | * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR |
| 253 | * contents are preserved across RESET when |
| 254 | * PWRGOOD it not deasserted. |
| 255 | */ |
| 256 | { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" }, |
| 257 | { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" }, |
| 258 | { BITVAL_EOT } |
| 259 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 260 | { BITS_EOT } |
| 261 | }}, |
| 262 | {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { |
| 263 | { BITS_EOT } |
| 264 | }}, |
| 265 | {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { |
| 266 | { BITS_EOT } |
| 267 | }}, |
| 268 | {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { |
| 269 | { BITS_EOT } |
| 270 | }}, |
| 271 | {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { |
| 272 | { BITS_EOT } |
| 273 | }}, |
| 274 | {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { |
| 275 | { BITS_EOT } |
| 276 | }}, |
| 277 | {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { |
| 278 | { BITS_EOT } |
| 279 | }}, |
| 280 | {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { |
| 281 | { BITS_EOT } |
| 282 | }}, |
| 283 | {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { |
| 284 | { BITS_EOT } |
| 285 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 286 | {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", |
| 287 | "BIOS Update Trigger Register (W)", { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 288 | { BITS_EOT } |
| 289 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 290 | {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", |
| 291 | "BIOS Update Signature ID (RO)", { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 292 | { BITS_EOT } |
| 293 | }}, |
| 294 | {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", { |
| 295 | { BITS_EOT } |
| 296 | }}, |
| 297 | {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", { |
| 298 | { BITS_EOT } |
| 299 | }}, |
| 300 | {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", "", { |
| 301 | { BITS_EOT } |
| 302 | }}, |
| 303 | {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", "", { |
| 304 | { BITS_EOT } |
| 305 | }}, |
| 306 | {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { |
| 307 | { BITS_EOT } |
| 308 | }}, |
| 309 | {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { |
| 310 | { BITS_EOT } |
| 311 | }}, |
| 312 | {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 313 | { 63, 52, RESERVED }, |
| 314 | { 11, 1, "SMRR Capability Using MSR 0xa0 and 0xa1", "R/O", PRESENT_BIN, { |
| 315 | { BITVAL_EOT } |
| 316 | }}, |
| 317 | { 10, 11, RESERVED }, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 318 | { BITS_EOT } |
| 319 | }}, |
| 320 | {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { |
| 321 | { BITS_EOT } |
| 322 | }}, |
| 323 | {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { |
| 324 | { BITS_EOT } |
| 325 | }}, |
| 326 | {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { |
| 327 | { BITS_EOT } |
| 328 | }}, |
| 329 | {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { |
| 330 | { BITS_EOT } |
| 331 | }}, |
| 332 | {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 333 | { 63, 61, RESERVED }, |
| 334 | { 2, 1, "MCIP", "R/W", PRESENT_BIN, { |
| 335 | /* When set, bit indicates that a machine check has been |
| 336 | * generated. If a second machine check is detected while |
| 337 | * this bit is still set, the processor enters a shutdown state. |
| 338 | * Software should write this bit to 0 after processing |
| 339 | * a machine check exception. |
| 340 | */ |
| 341 | { MSR1(0), "Nothing" }, |
| 342 | { MSR1(1), "Machine check has been generated" }, |
| 343 | { BITVAL_EOT } |
| 344 | }}, |
| 345 | { 1, 1, "EPIV", "R/W", PRESENT_BIN, { |
| 346 | /* When set, bit indicates that the instruction addressed |
| 347 | * by the instruction pointer pushed on the stack (when |
| 348 | * the machine check was generated) is directly associated |
| 349 | * with the error |
| 350 | */ |
| 351 | { MSR1(0), "Nothing" }, |
| 352 | { MSR1(1), "Instruction addressed directly associated with the error" }, |
| 353 | { BITVAL_EOT } |
| 354 | }}, |
| 355 | { 0, 1, "RIPV", "R/W", PRESENT_BIN, { |
| 356 | /* When set, bit indicates that the instruction addressed |
| 357 | * by the instruction pointer pushed on the stack (when |
| 358 | * the machine check was generated) can be used to restart |
| 359 | * the program. If cleared, the program cannot be reliably restarted |
| 360 | */ |
| 361 | { MSR1(0), "Program cannot be reliably restarted" }, |
| 362 | { MSR1(1), "Instruction addressed can be used to restart the program" }, |
| 363 | { BITVAL_EOT } |
| 364 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 365 | { BITS_EOT } |
| 366 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 367 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 368 | {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", |
| 369 | "Performance Event Select Register 0", { |
| 370 | { 63, 32, RESERVED }, |
| 371 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 372 | /* When CMASK is not zero, the corresponding performance |
| 373 | * counter 0 increments each cycle if the event count |
| 374 | * is greater than or equal to the CMASK. |
| 375 | */ |
| 376 | { BITVAL_EOT } |
| 377 | }}, |
| 378 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 379 | { MSR1(0), "CMASK using as is" }, |
| 380 | { MSR1(1), "CMASK inerting" }, |
| 381 | { BITVAL_EOT } |
| 382 | }}, |
| 383 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 384 | { MSR1(0), "No commence counting" }, |
| 385 | { MSR1(1), "Commence counting" }, |
| 386 | { BITVAL_EOT } |
| 387 | }}, |
| 388 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 389 | { BITVAL_EOT } |
| 390 | }}, |
| 391 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 392 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 393 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 394 | { BITVAL_EOT } |
| 395 | }}, |
| 396 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 397 | { MSR1(0), "Disabled pin control" }, |
| 398 | { MSR1(1), "Enabled pin control" }, |
| 399 | { BITVAL_EOT } |
| 400 | }}, |
| 401 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 402 | { MSR1(0), "Disabled edge detection" }, |
| 403 | { MSR1(1), "Enabled edge detection" }, |
| 404 | { BITVAL_EOT } |
| 405 | }}, |
| 406 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 407 | { MSR1(0), "Nothing" }, |
| 408 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 409 | { BITVAL_EOT } |
| 410 | }}, |
| 411 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 412 | { MSR1(0), "Nothing" }, |
| 413 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 414 | { BITVAL_EOT } |
| 415 | }}, |
| 416 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 417 | /* Qualifies the microarchitectural condition |
| 418 | * to detect on the selected event logic. */ |
| 419 | { BITVAL_EOT } |
| 420 | }}, |
| 421 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 422 | /* Selects a performance event logic unit. */ |
| 423 | { BITVAL_EOT } |
| 424 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 425 | { BITS_EOT } |
| 426 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 427 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 428 | {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", |
| 429 | "Performance Event Select Register 1", { |
| 430 | { 63, 32, RESERVED }, |
| 431 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 432 | /* When CMASK is not zero, the corresponding performance |
| 433 | * counter 1 increments each cycle if the event count |
| 434 | * is greater than or equal to the CMASK. |
| 435 | */ |
| 436 | { BITVAL_EOT } |
| 437 | }}, |
| 438 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 439 | { MSR1(0), "CMASK using as is" }, |
| 440 | { MSR1(1), "CMASK inerting" }, |
| 441 | { BITVAL_EOT } |
| 442 | }}, |
| 443 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 444 | { MSR1(0), "No commence counting" }, |
| 445 | { MSR1(1), "Commence counting" }, |
| 446 | { BITVAL_EOT } |
| 447 | }}, |
| 448 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 449 | { BITVAL_EOT } |
| 450 | }}, |
| 451 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 452 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 453 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 454 | { BITVAL_EOT } |
| 455 | }}, |
| 456 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 457 | { MSR1(0), "Disabled pin control" }, |
| 458 | { MSR1(1), "Enabled pin control" }, |
| 459 | { BITVAL_EOT } |
| 460 | }}, |
| 461 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 462 | { MSR1(0), "Disabled edge detection" }, |
| 463 | { MSR1(1), "Enabled edge detection" }, |
| 464 | { BITVAL_EOT } |
| 465 | }}, |
| 466 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 467 | { MSR1(0), "Nothing" }, |
| 468 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 469 | { BITVAL_EOT } |
| 470 | }}, |
| 471 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 472 | { MSR1(0), "Nothing" }, |
| 473 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 474 | { BITVAL_EOT } |
| 475 | }}, |
| 476 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 477 | /* Qualifies the microarchitectural condition |
| 478 | * to detect on the selected event logic. */ |
| 479 | { BITVAL_EOT } |
| 480 | }}, |
| 481 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 482 | /* Selects a performance event logic unit. */ |
| 483 | { BITVAL_EOT } |
| 484 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 485 | { BITS_EOT } |
| 486 | }}, |
| 487 | {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { |
| 488 | { BITS_EOT } |
| 489 | }}, |
| 490 | {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { |
| 491 | { BITS_EOT } |
| 492 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 493 | {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", |
| 494 | "Clock Modulation", { |
| 495 | { 63, 59, RESERVED }, |
| 496 | { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { |
| 497 | { MSR1(0), "On demand Clock Modulation is disabled" }, |
| 498 | { MSR1(1), "On demand Clock Modulation is enabled" }, |
| 499 | { BITVAL_EOT } |
| 500 | }}, |
| 501 | { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, { |
| 502 | { BITVAL_EOT } |
| 503 | }}, |
| 504 | { 0, 1, RESERVED }, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 505 | { BITS_EOT } |
| 506 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 507 | {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", |
| 508 | "Thermal Interrupt Control", { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 509 | { BITS_EOT } |
| 510 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 511 | {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", |
| 512 | "Thermal Monitor Status", { |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 513 | { BITS_EOT } |
| 514 | }}, |
| 515 | {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { |
| 516 | { BITS_EOT } |
| 517 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 518 | {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", |
| 519 | "Enable miscellaneous processor features", { |
| 520 | { 63, 24, RESERVED }, |
| 521 | { 39, 1, "IP Prefetcher Disable", "R/W", PRESENT_BIN, { |
| 522 | { MSR1(0), "IP Prefetcher enabled" }, |
| 523 | { MSR1(1), "IP Prefetcher disabled" }, |
| 524 | { BITVAL_EOT } |
| 525 | }}, |
| 526 | /* Note: [38] bit using for whole package, |
| 527 | * while some other bits can be Core or Thread |
| 528 | * specific. |
| 529 | */ |
| 530 | { 38, 1, "IDA Disable", "R/W", PRESENT_BIN, { |
| 531 | /* When set to a 0 on processors that support IDA, |
| 532 | * CPUID.06H: EAX[1] reports the processor's |
| 533 | * support of turbo mode is enabled. |
| 534 | */ |
| 535 | { MSR1(0), "IDA enabled" }, |
| 536 | /* When set 1 on processors that support Intel Turbo Boost |
| 537 | * technology, the turbo mode feature is disabled and |
| 538 | * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). |
| 539 | */ |
| 540 | { MSR1(1), "IDA disabled" }, |
| 541 | { BITVAL_EOT } |
| 542 | /* Note: the power-on default value is used by BIOS to detect |
| 543 | * hardware support of turbo mode. If power-on default value is 1, |
| 544 | * turbo mode is available in the processor. If power-on default |
| 545 | * value is 0, turbo mode not available. |
| 546 | */ |
| 547 | }}, |
| 548 | { 37, 1, "DCU Prefetcher Disable", "R/W", PRESENT_BIN, { |
| 549 | { MSR1(0), "DCU L1 data cache prefetcher is enabled" }, |
| 550 | { MSR1(1), "DCU L1 data cache prefetcher is disabled" }, |
| 551 | { BITVAL_EOT } |
| 552 | }}, |
| 553 | { 36, 2, RESERVED }, |
| 554 | { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, { |
| 555 | { BITVAL_EOT } |
| 556 | }}, |
| 557 | { 33, 10, RESERVED }, |
| 558 | { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, { |
| 559 | { BITVAL_EOT } |
| 560 | }}, |
| 561 | { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, { |
| 562 | { BITVAL_EOT } |
| 563 | }}, |
| 564 | { 21, 1, RESERVED }, |
| 565 | { 20, 1, "Enhanced Intel SpeedStep Select Lock", "R/W", |
| 566 | PRESENT_BIN, { |
| 567 | { MSR1(0), "Enhanced Intel SpeedStep Select\ |
| 568 | and Enable bits are writeable" }, |
| 569 | { MSR1(1), "Enhanced Intel SpeedStep Select\ |
| 570 | and Enable bits are locked and R/O" }, |
| 571 | { BITVAL_EOT } |
| 572 | }}, |
| 573 | { 19, 1, "Adjacent Cache Line Prefetch Disable", "R/W", |
| 574 | PRESENT_BIN, { |
| 575 | { MSR1(0), "Fetching cache lines that comprise a cache\ |
| 576 | line pair (128 bytes)" }, |
| 577 | { MSR1(1), "Fetching cache line that contains data\ |
| 578 | currently required by the processor" }, |
| 579 | { BITVAL_EOT } |
| 580 | }}, |
| 581 | { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, { |
| 582 | { BITVAL_EOT } |
| 583 | }}, |
| 584 | { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, { |
| 585 | { BITVAL_EOT } |
| 586 | }}, |
| 587 | /* Note: [16] bit using for whole package, |
| 588 | * while some other bits can be Core or Thread |
| 589 | * specific. |
| 590 | */ |
| 591 | { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W", |
| 592 | PRESENT_BIN, { |
| 593 | { BITVAL_EOT } |
| 594 | }}, |
| 595 | { 15, 2, RESERVED }, |
| 596 | { 13, 1, "TM2 Enable", "R/W", PRESENT_BIN, { |
| 597 | { BITVAL_EOT } |
| 598 | }}, |
| 599 | { 12, 1, "Precise Event Based Sampling Unavailable", "R/O", |
| 600 | PRESENT_BIN, { |
| 601 | { BITVAL_EOT } |
| 602 | }}, |
| 603 | { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, { |
| 604 | { BITVAL_EOT } |
| 605 | }}, |
| 606 | { 10, 1, "FERR# Multiplexing Enable", "R/W", PRESENT_BIN, { |
| 607 | { MSR1(0), "FERR# signaling compatible behaviour" }, |
| 608 | { MSR1(1), "FERR# asserted by the processor to indicate\ |
| 609 | a pending break event within the processor" }, |
| 610 | { BITVAL_EOT } |
| 611 | }}, |
| 612 | { 9, 1, "Hardware Prefetcher Disable", "R/W", PRESENT_BIN, { |
| 613 | { MSR1(0), "Hardware prefetcher is enabled" }, |
| 614 | { MSR1(1), "Hardware prefetcher is disabled" }, |
| 615 | { BITVAL_EOT } |
| 616 | }}, |
| 617 | { 8, 1, RESERVED }, |
| 618 | { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, { |
| 619 | { BITVAL_EOT } |
| 620 | }}, |
| 621 | { 6, 3, RESERVED }, |
| 622 | { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W" |
| 623 | , PRESENT_BIN, { |
| 624 | { BITVAL_EOT } |
| 625 | }}, |
| 626 | { 2, 2, RESERVED }, |
| 627 | { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, { |
| 628 | { BITVAL_EOT } |
| 629 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 630 | { BITS_EOT } |
| 631 | }}, |
| 632 | {0x1c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", { |
| 633 | { BITS_EOT } |
| 634 | }}, |
| 635 | {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { |
| 636 | { BITS_EOT } |
| 637 | }}, |
| 638 | {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { |
| 639 | { BITS_EOT } |
| 640 | }}, |
| 641 | {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { |
| 642 | { BITS_EOT } |
| 643 | }}, |
| 644 | {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { |
| 645 | { BITS_EOT } |
| 646 | }}, |
| 647 | {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { |
| 648 | { BITS_EOT } |
| 649 | }}, |
| 650 | {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { |
| 651 | { BITS_EOT } |
| 652 | }}, |
| 653 | {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { |
| 654 | { BITS_EOT } |
| 655 | }}, |
| 656 | {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { |
| 657 | { BITS_EOT } |
| 658 | }}, |
| 659 | {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { |
| 660 | { BITS_EOT } |
| 661 | }}, |
| 662 | {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { |
| 663 | { BITS_EOT } |
| 664 | }}, |
| 665 | {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { |
| 666 | { BITS_EOT } |
| 667 | }}, |
| 668 | {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { |
| 669 | { BITS_EOT } |
| 670 | }}, |
| 671 | {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { |
| 672 | { BITS_EOT } |
| 673 | }}, |
| 674 | {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { |
| 675 | { BITS_EOT } |
| 676 | }}, |
| 677 | {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { |
| 678 | { BITS_EOT } |
| 679 | }}, |
| 680 | {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { |
| 681 | { BITS_EOT } |
| 682 | }}, |
| 683 | {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { |
| 684 | { BITS_EOT } |
| 685 | }}, |
| 686 | {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { |
| 687 | { BITS_EOT } |
| 688 | }}, |
| 689 | {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { |
| 690 | { BITS_EOT } |
| 691 | }}, |
| 692 | {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { |
| 693 | { BITS_EOT } |
| 694 | }}, |
| 695 | {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { |
| 696 | { BITS_EOT } |
| 697 | }}, |
| 698 | {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { |
| 699 | { BITS_EOT } |
| 700 | }}, |
| 701 | {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { |
| 702 | { BITS_EOT } |
| 703 | }}, |
| 704 | {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { |
| 705 | { BITS_EOT } |
| 706 | }}, |
| 707 | {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { |
| 708 | { BITS_EOT } |
| 709 | }}, |
| 710 | {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { |
| 711 | { BITS_EOT } |
| 712 | }}, |
| 713 | {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { |
| 714 | { BITS_EOT } |
| 715 | }}, |
| 716 | {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { |
| 717 | { BITS_EOT } |
| 718 | }}, |
| 719 | {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { |
| 720 | { BITS_EOT } |
| 721 | }}, |
| 722 | {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { |
| 723 | { BITS_EOT } |
| 724 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 725 | {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { |
| 726 | { 63, 5, RESERVED }, |
| 727 | { 58, 3, "PA7", "R/W", PRESENT_BIN, { |
| 728 | { BITVAL_EOT } |
| 729 | }}, |
| 730 | { 55, 5, RESERVED }, |
| 731 | { 40, 3, "PA6", "R/W", PRESENT_BIN, { |
| 732 | { BITVAL_EOT } |
| 733 | }}, |
| 734 | { 47, 5, RESERVED }, |
| 735 | { 42, 3, "PA5", "R/W", PRESENT_BIN, { |
| 736 | { BITVAL_EOT } |
| 737 | }}, |
| 738 | { 39, 5, RESERVED }, |
| 739 | { 34, 3, "PA4", "R/W", PRESENT_BIN, { |
| 740 | { BITVAL_EOT } |
| 741 | }}, |
| 742 | { 31, 5, RESERVED }, |
| 743 | { 26, 3, "PA3", "R/W", PRESENT_BIN, { |
| 744 | { BITVAL_EOT } |
| 745 | }}, |
| 746 | { 23, 5, RESERVED }, |
| 747 | { 18, 3, "PA2", "R/W", PRESENT_BIN, { |
| 748 | { BITVAL_EOT } |
| 749 | }}, |
| 750 | { 15, 5, RESERVED }, |
| 751 | { 10, 3, "PA1", "R/W", PRESENT_BIN, { |
| 752 | { BITVAL_EOT } |
| 753 | }}, |
| 754 | { 7, 5, RESERVED }, |
| 755 | { 2, 3, "PA0", "R/W", PRESENT_BIN, { |
| 756 | { BITVAL_EOT } |
| 757 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 758 | { BITS_EOT } |
| 759 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 760 | {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", |
| 761 | "Default Memory Types", { |
| 762 | { 63, 52, RESERVED }, |
| 763 | { 11, 1, "MTRR Enable", "R/W", PRESENT_BIN, { |
| 764 | { BITVAL_EOT } |
| 765 | }}, |
| 766 | { 10, 1, "Fixed Range MTRR Enable", "R/W", PRESENT_BIN, { |
| 767 | { BITVAL_EOT } |
| 768 | }}, |
| 769 | { 9, 7, RESERVED }, |
| 770 | { 2, 3, "Default Memory Type", "R/W", PRESENT_HEX, { |
| 771 | { BITVAL_EOT } |
| 772 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 773 | { BITS_EOT } |
| 774 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 775 | /* if CPUID.0AH: EDX[4:0] > 0 */ |
| 776 | {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ |
| 777 | Performance Counter Register 0: Counts Instr_Retired.Any", { |
| 778 | /* Also known as MSR_PERF_FIXED_CTR0 */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 779 | { BITS_EOT } |
| 780 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 781 | /* if CPUID.0AH: EDX[4:0] > 1 */ |
| 782 | {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ |
| 783 | Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { |
| 784 | /* Also known as MSR_PERF_FIXED_CTR1 */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 785 | { BITS_EOT } |
| 786 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 787 | /* if CPUID.0AH: EDX[4:0] > 2 */ |
| 788 | {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ |
| 789 | Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { |
| 790 | /* Also known as MSR_PERF_FIXED_CTR2 */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 791 | { BITS_EOT } |
| 792 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 793 | {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { |
| 794 | /* Additional info available at Section 17.4.1 of |
| 795 | * Intel 64 and IA-32 Architecures Software Developer's |
| 796 | * Manual, Volume 3. |
| 797 | */ |
| 798 | { 63, 56, RESERVED }, |
| 799 | { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, { |
| 800 | { BITVAL_EOT } |
| 801 | }}, |
| 802 | { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, { |
| 803 | { BITVAL_EOT } |
| 804 | }}, |
| 805 | { 5, 6, "LBR Format", "R/O", PRESENT_HEX, { |
| 806 | { BITVAL_EOT } |
| 807 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 808 | { BITS_EOT } |
| 809 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 810 | /* if CPUID.0AH: EAX[7:0] > 1*/ |
| 811 | {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", |
| 812 | "Fixed-Function-Counter Control Register", { |
| 813 | /* Also known as MSR_PERF_FIXED_CTR_CTRL. |
| 814 | * Counter increments while the results of ANDing respective enable bit |
| 815 | * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits |
| 816 | * in this MSR is true. */ |
| 817 | { 63, 52, RESERVED }, |
| 818 | { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, { |
| 819 | { MSR1(0), "Nothing" }, |
| 820 | { MSR1(1), "PMI when fixed counter 2 overflows is enabled" }, |
| 821 | { BITVAL_EOT } |
| 822 | }}, |
| 823 | /* if CPUID.0AH EAX[7:0] > 2 */ |
| 824 | { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { |
| 825 | { MSR1(0), "Counter only increments the associated event \ |
| 826 | conditions occuring in the logical processor which programmed the MSR" }, |
| 827 | { MSR1(1), "Counting the associated event conditions \ |
| 828 | occuring across all logical processors sharing a processor core" }, |
| 829 | { BITVAL_EOT } |
| 830 | }}, |
| 831 | { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { |
| 832 | { MSR1(0), "Nothing" }, |
| 833 | { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" }, |
| 834 | { BITVAL_EOT } |
| 835 | }}, |
| 836 | { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, { |
| 837 | { MSR1(0), "Nothing" }, |
| 838 | { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" }, |
| 839 | { BITVAL_EOT } |
| 840 | }}, |
| 841 | { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, { |
| 842 | { MSR1(0), "Nothing" }, |
| 843 | { MSR1(1), "PMI when fixed counter 1 overflows is enabled" }, |
| 844 | { BITVAL_EOT } |
| 845 | }}, |
| 846 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 847 | { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { |
| 848 | { MSR1(0), "Counter only increments the associated event \ |
| 849 | conditions occuring in the logical processor which programmed the MSR" }, |
| 850 | { MSR1(1), "Counting the associated event conditions \ |
| 851 | occuring across all logical processors sharing a processor core" }, |
| 852 | { BITVAL_EOT } |
| 853 | }}, |
| 854 | { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { |
| 855 | { MSR1(0), "Nothing" }, |
| 856 | { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" }, |
| 857 | { BITVAL_EOT } |
| 858 | }}, |
| 859 | { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, { |
| 860 | { MSR1(0), "Nothing" }, |
| 861 | { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" }, |
| 862 | { BITVAL_EOT } |
| 863 | }}, |
| 864 | { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, { |
| 865 | { MSR1(0), "Nothing" }, |
| 866 | { MSR1(1), "PMI when fixed counter 0 overflows is enabled" }, |
| 867 | { BITVAL_EOT } |
| 868 | }}, |
| 869 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 870 | { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { |
| 871 | { MSR1(0), "Counter only increments the associated event \ |
| 872 | conditions occuring in the logical processor which programmed the MSR" }, |
| 873 | { MSR1(1), "Counting the associated event conditions \ |
| 874 | occuring across all logical processors sharing a processor core" }, |
| 875 | { BITVAL_EOT } |
| 876 | }}, |
| 877 | { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { |
| 878 | { MSR1(0), "Nothing" }, |
| 879 | { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" }, |
| 880 | { BITVAL_EOT } |
| 881 | }}, |
| 882 | { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, { |
| 883 | { MSR1(0), "Nothing" }, |
| 884 | { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" }, |
| 885 | { BITVAL_EOT } |
| 886 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 887 | { BITS_EOT } |
| 888 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 889 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 890 | {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", |
| 891 | "Global Performance Counter Status", { |
| 892 | /* Also known as MSR_PERF_GLOBAL_STATUS */ |
| 893 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 894 | { 63, 1, "CondChg: Status bits of this register has changed", |
| 895 | "R/O", PRESENT_BIN, { |
| 896 | { BITVAL_EOT } |
| 897 | }}, |
| 898 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 899 | { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status", |
| 900 | "R/O", PRESENT_BIN, { |
| 901 | { BITVAL_EOT } |
| 902 | }}, |
| 903 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 904 | { 61, 1, "Ovf_Uncore: Uncore counter overflow status", |
| 905 | "R/O", PRESENT_BIN, { |
| 906 | { BITVAL_EOT } |
| 907 | }}, |
| 908 | { 60, 26, RESERVED }, |
| 909 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 910 | { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2", |
| 911 | "R/O", PRESENT_BIN, { |
| 912 | { BITVAL_EOT } |
| 913 | }}, |
| 914 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 915 | { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1", |
| 916 | "R/O", PRESENT_BIN, { |
| 917 | { BITVAL_EOT } |
| 918 | }}, |
| 919 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 920 | { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0", |
| 921 | "R/O", PRESENT_BIN, { |
| 922 | { BITVAL_EOT } |
| 923 | }}, |
| 924 | { 31, 28, RESERVED }, |
| 925 | /* presented only in 06_2EH Nehalem model */ |
| 926 | { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, { |
| 927 | { BITVAL_EOT } |
| 928 | }}, |
| 929 | /* presented only in 06_2EH Nehalem model */ |
| 930 | { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, { |
| 931 | { BITVAL_EOT } |
| 932 | }}, |
| 933 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 934 | { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, { |
| 935 | { BITVAL_EOT } |
| 936 | }}, |
| 937 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 938 | { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, { |
| 939 | { BITVAL_EOT } |
| 940 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 941 | { BITS_EOT } |
| 942 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 943 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 944 | {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", |
| 945 | "Global Performance Counter Control", { |
| 946 | /* Counter increments while the result of ANDing respective |
| 947 | * enable bit in this MSR with corresponding OS or USR bits |
| 948 | * in general-purpose or fixed counter control MSR is true. |
| 949 | */ |
| 950 | { 63, 29, RESERVED }, |
| 951 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 952 | { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, { |
| 953 | { BITVAL_EOT } |
| 954 | }}, |
| 955 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 956 | { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, { |
| 957 | { BITVAL_EOT } |
| 958 | }}, |
| 959 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 960 | { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, { |
| 961 | { BITVAL_EOT } |
| 962 | }}, |
| 963 | { 31, 30, RESERVED }, |
| 964 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 965 | { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, { |
| 966 | { BITVAL_EOT } |
| 967 | }}, |
| 968 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 969 | { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, { |
| 970 | { BITVAL_EOT } |
| 971 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 972 | { BITS_EOT } |
| 973 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 974 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 975 | {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", |
| 976 | "Global Performance Counter Overflow Control", { |
| 977 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 978 | { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { |
| 979 | { BITVAL_EOT } |
| 980 | }}, |
| 981 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 982 | { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, { |
| 983 | { BITVAL_EOT } |
| 984 | }}, |
| 985 | /* Presented only in 06_2EH Nehalem model */ |
| 986 | { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, { |
| 987 | { BITVAL_EOT } |
| 988 | }}, |
| 989 | { 60, 26, RESERVED }, |
| 990 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 991 | { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, { |
| 992 | { BITVAL_EOT } |
| 993 | }}, |
| 994 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 995 | { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, { |
| 996 | { BITVAL_EOT } |
| 997 | }}, |
| 998 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 999 | { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, { |
| 1000 | { BITVAL_EOT } |
| 1001 | }}, |
| 1002 | { 31, 30, RESERVED }, |
| 1003 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1004 | { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, { |
| 1005 | { BITVAL_EOT } |
| 1006 | }}, |
| 1007 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1008 | { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, { |
| 1009 | { BITVAL_EOT } |
| 1010 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1011 | { BITS_EOT } |
| 1012 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1013 | /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures |
| 1014 | * Software Developer's Manual, Volume 3, |
| 1015 | * "Precise Event Based Sampling (PEBS)". |
| 1016 | */ |
| 1017 | {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { |
| 1018 | { 63, 28, RESERVED }, |
| 1019 | { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { |
| 1020 | { MSR1(0), "Disabled" }, |
| 1021 | { MSR1(1), "Enabled" }, |
| 1022 | { BITVAL_EOT } |
| 1023 | }}, |
| 1024 | { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, { |
| 1025 | { MSR1(0), "Disabled" }, |
| 1026 | { MSR1(1), "Enabled" }, |
| 1027 | { BITVAL_EOT } |
| 1028 | }}, |
| 1029 | { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, { |
| 1030 | { MSR1(0), "Disabled" }, |
| 1031 | { MSR1(1), "Enabled" }, |
| 1032 | { BITVAL_EOT } |
| 1033 | }}, |
| 1034 | { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, { |
| 1035 | { MSR1(0), "Disabled" }, |
| 1036 | { MSR1(1), "Enabled" }, |
| 1037 | { BITVAL_EOT } |
| 1038 | }}, |
| 1039 | { 31, 28, RESERVED }, |
| 1040 | { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, { |
| 1041 | { MSR1(0), "Disabled" }, |
| 1042 | { MSR1(1), "Enabled" }, |
| 1043 | { BITVAL_EOT } |
| 1044 | }}, |
| 1045 | { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, { |
| 1046 | { MSR1(0), "Disabled" }, |
| 1047 | { MSR1(1), "Enabled" }, |
| 1048 | { BITVAL_EOT } |
| 1049 | }}, |
| 1050 | { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, { |
| 1051 | { MSR1(0), "Disabled" }, |
| 1052 | { MSR1(1), "Enabled" }, |
| 1053 | { BITVAL_EOT } |
| 1054 | }}, |
| 1055 | { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, { |
| 1056 | { MSR1(0), "Disabled" }, |
| 1057 | { MSR1(1), "Enabled" }, |
| 1058 | { BITVAL_EOT } |
| 1059 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1060 | { BITS_EOT } |
| 1061 | }}, |
| 1062 | {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { |
| 1063 | { BITS_EOT } |
| 1064 | }}, |
| 1065 | {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { |
| 1066 | { BITS_EOT } |
| 1067 | }}, |
| 1068 | {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { |
| 1069 | { BITS_EOT } |
| 1070 | }}, |
| 1071 | {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { |
| 1072 | { BITS_EOT } |
| 1073 | }}, |
| 1074 | {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { |
| 1075 | { BITS_EOT } |
| 1076 | }}, |
| 1077 | {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { |
| 1078 | { BITS_EOT } |
| 1079 | }}, |
| 1080 | {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { |
| 1081 | { BITS_EOT } |
| 1082 | }}, |
| 1083 | {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { |
| 1084 | { BITS_EOT } |
| 1085 | }}, |
| 1086 | {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { |
| 1087 | { BITS_EOT } |
| 1088 | }}, |
| 1089 | {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { |
| 1090 | { BITS_EOT } |
| 1091 | }}, |
| 1092 | {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { |
| 1093 | { BITS_EOT } |
| 1094 | }}, |
| 1095 | {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { |
| 1096 | { BITS_EOT } |
| 1097 | }}, |
| 1098 | {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { |
| 1099 | { BITS_EOT } |
| 1100 | }}, |
| 1101 | {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { |
| 1102 | { BITS_EOT } |
| 1103 | }}, |
| 1104 | {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { |
| 1105 | { BITS_EOT } |
| 1106 | }}, |
| 1107 | {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { |
| 1108 | { BITS_EOT } |
| 1109 | }}, |
| 1110 | {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { |
| 1111 | { BITS_EOT } |
| 1112 | }}, |
| 1113 | {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { |
| 1114 | { BITS_EOT } |
| 1115 | }}, |
| 1116 | {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { |
| 1117 | { BITS_EOT } |
| 1118 | }}, |
| 1119 | {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { |
| 1120 | { BITS_EOT } |
| 1121 | }}, |
| 1122 | {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { |
| 1123 | { BITS_EOT } |
| 1124 | }}, |
| 1125 | {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", { |
| 1126 | { BITS_EOT } |
| 1127 | }}, |
| 1128 | {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", { |
| 1129 | { BITS_EOT } |
| 1130 | }}, |
| 1131 | {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", { |
| 1132 | { BITS_EOT } |
| 1133 | }}, |
| 1134 | {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", { |
| 1135 | { BITS_EOT } |
| 1136 | }}, |
| 1137 | {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", { |
| 1138 | { BITS_EOT } |
| 1139 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1140 | {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", |
| 1141 | "Reporting Register of Basic VMX Capabilities", { |
| 1142 | /* Additional info available at |
| 1143 | * Appendix A.1, "Basic VMX Information" */ |
| 1144 | { 63, 10, RESERVED }, |
| 1145 | { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, { |
| 1146 | { BITVAL_EOT } |
| 1147 | }}, |
| 1148 | { 49, 1, "Support of dual-treatment of system-management functions", |
| 1149 | "R/O", PRESENT_BIN, { |
| 1150 | { BITVAL_EOT } |
| 1151 | }}, |
| 1152 | { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, { |
| 1153 | { BITVAL_EOT } |
| 1154 | }}, |
| 1155 | { 47, 3, RESERVED }, |
| 1156 | { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, { |
| 1157 | { BITVAL_EOT } |
| 1158 | }}, |
| 1159 | { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, { |
| 1160 | { BITVAL_EOT } |
| 1161 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1162 | { BITS_EOT } |
| 1163 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1164 | {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", |
| 1165 | "Capability Reporting Register of \ |
| 1166 | Pin-based VM-execution Controls", { |
| 1167 | /* Additional info available at Appendix A.3, |
| 1168 | * "VM-Execution Controls" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1169 | { BITS_EOT } |
| 1170 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1171 | {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", |
| 1172 | "Capability Reporting Register of \ |
| 1173 | Primary Processor-based VM-execution Controls", { |
| 1174 | /* Additional info available at Appendix A.3, |
| 1175 | * "VM-Execution Controls" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1176 | { BITS_EOT } |
| 1177 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1178 | {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", |
| 1179 | "Capability Reporting Register of VM-exit Controls", { |
| 1180 | /* Additional info available at Appendix A.4, |
| 1181 | * "VM-Exit Controls" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1182 | { BITS_EOT } |
| 1183 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1184 | {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", |
| 1185 | "Capability Reporting Register of VM-entry Controls", { |
| 1186 | /* Additional info available at Appendix A.5, |
| 1187 | * "VM-Entry Controls" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1188 | { BITS_EOT } |
| 1189 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1190 | {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", |
| 1191 | "Reporting Register of Miscellaneous VMX Capabilities", { |
| 1192 | /* Additional info available at Appendix A.6, |
| 1193 | * "Miscellaneous Data" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1194 | { BITS_EOT } |
| 1195 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1196 | {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", |
| 1197 | "Capability Reporting Register of CR0 Bits Fixed to 0", { |
| 1198 | /* Additional info available at Appendix A.7, |
| 1199 | * "VMX-Fixed Bits in CR0" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1200 | { BITS_EOT } |
| 1201 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1202 | {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", |
| 1203 | "Capability Reporting Register of CR0 Bits Fixed to 1", { |
| 1204 | /* Additional info available at Appendix A.7, |
| 1205 | * "VMX-Fixed Bits in CR0" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1206 | { BITS_EOT } |
| 1207 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1208 | {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", |
| 1209 | "Capability Reporting Register of CR4 Bits Fixed to 0", { |
| 1210 | /* Additional info available at Appendix A.8, |
| 1211 | * "VMX-Fixed Bits in CR4" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1212 | { BITS_EOT } |
| 1213 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1214 | {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", |
| 1215 | "Capability Reporting Register of CR4 Bits Fixed to 1", { |
| 1216 | /* Additional info available at Appendix A.8, |
| 1217 | * "VMX-Fixed Bits in CR4" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1218 | { BITS_EOT } |
| 1219 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1220 | {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", |
| 1221 | "Capability Reporting Register of VMCS Field Enumeration", { |
| 1222 | /* Additional info available at Appendix A.9, |
| 1223 | * "VMCS Enumeration" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1224 | { BITS_EOT } |
| 1225 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1226 | {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", |
| 1227 | "Capability Reporting Register of Secondary \ |
| 1228 | Processor-based VM-execution Controls", { |
| 1229 | /* Additional info available at Appendix A.3, |
| 1230 | * "VM-Execution Controls" */ |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1231 | { BITS_EOT } |
| 1232 | }}, |
Anton Kochkov | dd678a2 | 2012-07-04 07:39:07 +0400 | [diff] [blame] | 1233 | {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { |
| 1234 | /* Additional info available at Section 18.10.4 of Intel 64 |
| 1235 | * and IA-32 Architectures Software Developer's Manual, |
| 1236 | * "Debug Store (DS) Mechanism". |
| 1237 | */ |
| 1238 | { 63, 32, RESERVED }, // reserved if not in IA-32e mode |
| 1239 | { 31, 32, "Linear address of DS buffer management area", |
| 1240 | "R/W", PRESENT_HEX, { |
| 1241 | { BITVAL_EOT } |
| 1242 | }}, |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1243 | { BITS_EOT } |
| 1244 | }}, |
| 1245 | {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", { |
| 1246 | { BITS_EOT } |
| 1247 | }}, |
| 1248 | {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", { |
| 1249 | { BITS_EOT } |
| 1250 | }}, |
| 1251 | {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", { |
| 1252 | { BITS_EOT } |
| 1253 | }}, |
| 1254 | {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", { |
| 1255 | { BITS_EOT } |
| 1256 | }}, |
| 1257 | {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", { |
| 1258 | { BITS_EOT } |
| 1259 | }}, |
| 1260 | {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", { |
| 1261 | { BITS_EOT } |
| 1262 | }}, |
| 1263 | {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", { |
| 1264 | { BITS_EOT } |
| 1265 | }}, |
| 1266 | {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", { |
| 1267 | { BITS_EOT } |
| 1268 | }}, |
| 1269 | {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", { |
| 1270 | { BITS_EOT } |
| 1271 | }}, |
| 1272 | {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", "", { |
| 1273 | { BITS_EOT } |
| 1274 | }}, |
| 1275 | {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", "", { |
| 1276 | { BITS_EOT } |
| 1277 | }}, |
| 1278 | {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", "", { |
| 1279 | { BITS_EOT } |
| 1280 | }}, |
| 1281 | {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", "", { |
| 1282 | { BITS_EOT } |
| 1283 | }}, |
| 1284 | {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", "", { |
| 1285 | { BITS_EOT } |
| 1286 | }}, |
| 1287 | {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", "", { |
| 1288 | { BITS_EOT } |
| 1289 | }}, |
| 1290 | {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", "", { |
| 1291 | { BITS_EOT } |
| 1292 | }}, |
| 1293 | { MSR_EOT } |
| 1294 | }; |
| 1295 | |
| 1296 | |