Aaron Durbin | 029aaf6 | 2013-10-10 12:41:49 -0500 | [diff] [blame^] | 1 | |
| 2 | /* |
| 3 | * This file is part of the coreboot project. |
| 4 | * |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | #ifndef CPU_X86_CR_H |
| 21 | #define CPU_X86_CR_H |
| 22 | |
| 23 | #if !defined(__ASSEMBLER__) |
| 24 | |
| 25 | #include <stdint.h> |
| 26 | #include <arch/cpu.h> |
| 27 | |
| 28 | /* ROMCC apparently chokes certain clobber registers. */ |
| 29 | #if defined(__ROMCC__) |
| 30 | #define COMPILER_BARRIER |
| 31 | #else |
| 32 | #define COMPILER_BARRIER "memory" |
| 33 | #endif |
| 34 | |
| 35 | static alwaysinline uint32_t read_cr0(void) |
| 36 | { |
| 37 | uint32_t value; |
| 38 | __asm__ __volatile__ ( |
| 39 | "mov %%cr0, %0" |
| 40 | : "=r" (value) |
| 41 | : |
| 42 | : COMPILER_BARRIER |
| 43 | ); |
| 44 | return value; |
| 45 | } |
| 46 | |
| 47 | static alwaysinline void write_cr0(uint32_t data) |
| 48 | { |
| 49 | __asm__ __volatile__ ( |
| 50 | "mov %0, %%cr0" |
| 51 | : |
| 52 | : "r" (data) |
| 53 | : COMPILER_BARRIER |
| 54 | ); |
| 55 | } |
| 56 | |
| 57 | static alwaysinline uint32_t read_cr4(void) |
| 58 | { |
| 59 | uint32_t value; |
| 60 | __asm__ __volatile__ ( |
| 61 | "mov %%cr4, %0" |
| 62 | : "=r" (value) |
| 63 | : |
| 64 | : COMPILER_BARRIER |
| 65 | ); |
| 66 | return value; |
| 67 | } |
| 68 | |
| 69 | static alwaysinline void write_cr4(uint32_t data) |
| 70 | { |
| 71 | __asm__ __volatile__ ( |
| 72 | "mov %0, %%cr4" |
| 73 | : |
| 74 | : "r" (data) |
| 75 | : COMPILER_BARRIER |
| 76 | ); |
| 77 | } |
| 78 | |
| 79 | #endif /* !defined(__ASSEMBLER__) */ |
| 80 | |
| 81 | /* CR0 flags */ |
| 82 | #define CR0_PE (1 << 0) |
| 83 | #define CR0_MP (1 << 1) |
| 84 | #define CR0_EM (1 << 2) |
| 85 | #define CR0_TS (1 << 3) |
| 86 | #define CR0_ET (1 << 4) |
| 87 | #define CR0_NE (1 << 5) |
| 88 | #define CR0_WP (1 << 16) |
| 89 | #define CR0_AM (1 << 18) |
| 90 | #define CR0_NW (1 << 29) |
| 91 | #define CR0_CD (1 << 30) |
| 92 | #define CR0_PG (1 << 31) |
| 93 | |
| 94 | /* CR4 flags */ |
| 95 | #define CR4_VME (1 << 0) |
| 96 | #define CR4_PVI (1 << 1) |
| 97 | #define CR4_TSD (1 << 2) |
| 98 | #define CR4_DE (1 << 3) |
| 99 | #define CR4_PSE (1 << 4) |
| 100 | #define CR4_PAE (1 << 5) |
| 101 | #define CR4_MCE (1 << 6) |
| 102 | #define CR4_PGE (1 << 7) |
| 103 | #define CR4_PCE (1 << 8) |
| 104 | #define CR4_OSFXSR (1 << 9) |
| 105 | #define CR4_OSXMMEXCPT (1 << 10) |
| 106 | #define CR4_VMXE (1 << 13) |
| 107 | #define CR4_SMXE (1 << 14) |
| 108 | #define CR4_FSGSBASE (1 << 16) |
| 109 | #define CR4_PCIDE (1 << 17) |
| 110 | #define CR4_OSXSAVE (1 << 18) |
| 111 | #define CR4_SMEP (1 << 20) |
| 112 | |
| 113 | #endif /* CPU_X86_CR_H */ |