Patrick Georgi | 02363b5 | 2020-05-05 20:48:50 +0200 | [diff] [blame^] | 1 | /* This file is part of the coreboot project. */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 2 | /* |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation; either version 2 of |
| 7 | * the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H |
| 16 | #define NORTHBRIDGE_INTEL_PINEVIEW_H |
| 17 | |
| 18 | #include <northbridge/intel/pineview/iomap.h> |
| 19 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 20 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 21 | #define BOOT_PATH_NORMAL 0 |
| 22 | #define BOOT_PATH_RESET 1 |
| 23 | #define BOOT_PATH_RESUME 2 |
| 24 | |
| 25 | #define SYSINFO_DIMM_NOT_POPULATED 0x00 |
| 26 | #define SYSINFO_DIMM_X16SS 0x01 |
| 27 | #define SYSINFO_DIMM_X16DS 0x02 |
| 28 | #define SYSINFO_DIMM_X8DS 0x05 |
| 29 | #define SYSINFO_DIMM_X8DDS 0x06 |
| 30 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 31 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 32 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 33 | |
| 34 | #define EPBAR 0x40 |
| 35 | #define MCHBAR 0x48 |
| 36 | #define PCIEXBAR 0x60 |
| 37 | #define DMIBAR 0x68 |
| 38 | #define PMIOBAR 0x78 |
| 39 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 40 | #define GGC 0x52 /* GMCH Graphics Control */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 41 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 42 | #define DEVEN 0x54 /* Device Enable */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 43 | #define DEVEN_D0F0 (1 << 0) |
| 44 | #define DEVEN_D1F0 (1 << 1) |
| 45 | #define DEVEN_D2F0 (1 << 3) |
| 46 | #define DEVEN_D2F1 (1 << 4) |
| 47 | |
| 48 | #ifndef BOARD_DEVEN |
| 49 | #define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) |
| 50 | #endif /* BOARD_DEVEN */ |
| 51 | |
| 52 | #define PAM0 0x90 |
| 53 | #define PAM1 0x91 |
| 54 | #define PAM2 0x92 |
| 55 | #define PAM3 0x93 |
| 56 | #define PAM4 0x94 |
| 57 | #define PAM5 0x95 |
| 58 | #define PAM6 0x96 |
| 59 | |
| 60 | #define LAC 0x97 /* Legacy Access Control */ |
| 61 | #define REMAPBASE 0x98 |
| 62 | #define REMAPLIMIT 0x9a |
| 63 | #define SMRAM 0x9d /* System Management RAM Control */ |
Arthur Heymans | 4bdfebd | 2018-04-09 22:10:33 +0200 | [diff] [blame] | 64 | #define ESMRAMC 0x9e /* Extended System Management RAM Control */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 65 | |
| 66 | #define TOM 0xa0 |
| 67 | #define TOUUD 0xa2 |
| 68 | #define GBSM 0xa4 |
| 69 | #define BGSM 0xa8 |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 70 | #define TSEG 0xac |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 71 | #define TOLUD 0xb0 /* Top of Low Used Memory */ |
| 72 | #define ERRSTS 0xc8 |
| 73 | #define ERRCMD 0xca |
| 74 | #define SMICMD 0xcc |
| 75 | #define SCICMD 0xce |
| 76 | #define CGDIS 0xd8 |
| 77 | #define SKPAD 0xdc /* Scratchpad Data */ |
| 78 | #define CAPID0 0xe0 |
| 79 | #define DEV0T 0xf0 |
| 80 | #define MSLCK 0xf4 |
| 81 | #define MID0 0xf8 |
| 82 | #define DEBUP0 0xfc |
| 83 | |
| 84 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 85 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 86 | #define PEGSTS 0x214 /* 32 bits */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 87 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 88 | /* Device 0:2.0 PCI configuration space (Integrated Graphics Device) */ |
| 89 | #define GMCH_IGD PCI_DEV(0, 2, 0) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 90 | |
| 91 | #define GMADR 0x18 |
| 92 | #define GTTADR 0x1c |
| 93 | #define BSM 0x5c |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 94 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 95 | #define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x)) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * MCHBAR |
| 99 | */ |
| 100 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 101 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
| 102 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
| 103 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ |
| 104 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 105 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 106 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 107 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 108 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 109 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 110 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 111 | #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
| 112 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
| 113 | |
| 114 | /* As there are many registers, define them on a separate file */ |
| 115 | |
| 116 | #include "mchbar_regs.h" |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 117 | |
| 118 | /* |
| 119 | * EPBAR - Egress Port Root Complex Register Block |
| 120 | */ |
| 121 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 122 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 123 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) |
| 124 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) |
| 125 | |
| 126 | /* |
| 127 | * DMIBAR |
| 128 | */ |
| 129 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 130 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 131 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) |
| 132 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) |
| 133 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 134 | enum fsb_clk { |
| 135 | FSB_CLOCK_667MHz = 0, |
| 136 | FSB_CLOCK_800MHz = 1, |
| 137 | }; |
| 138 | |
| 139 | enum mem_clk { |
| 140 | MEM_CLOCK_667MHz = 0, |
| 141 | MEM_CLOCK_800MHz = 1, |
| 142 | }; |
| 143 | |
| 144 | enum ddr { |
| 145 | DDR2 = 2, |
| 146 | DDR3 = 3, |
| 147 | }; |
| 148 | |
| 149 | enum chip_width { /* as in DDR3 spd */ |
| 150 | CHIP_WIDTH_x4 = 0, |
| 151 | CHIP_WIDTH_x8 = 1, |
| 152 | CHIP_WIDTH_x16 = 2, |
| 153 | CHIP_WIDTH_x32 = 3, |
| 154 | }; |
| 155 | |
| 156 | enum chip_cap { /* as in DDR3 spd */ |
| 157 | CHIP_CAP_256M = 0, |
| 158 | CHIP_CAP_512M = 1, |
| 159 | CHIP_CAP_1G = 2, |
| 160 | CHIP_CAP_2G = 3, |
| 161 | CHIP_CAP_4G = 4, |
| 162 | CHIP_CAP_8G = 5, |
| 163 | CHIP_CAP_16G = 6, |
| 164 | }; |
| 165 | |
| 166 | struct timings { |
| 167 | unsigned int CAS; |
| 168 | enum fsb_clk fsb_clock; |
| 169 | enum mem_clk mem_clock; |
| 170 | unsigned int tRAS; |
| 171 | unsigned int tRP; |
| 172 | unsigned int tRCD; |
| 173 | unsigned int tWR; |
| 174 | unsigned int tRFC; |
| 175 | unsigned int tWTR; |
| 176 | unsigned int tRRD; |
| 177 | unsigned int tRTP; |
| 178 | }; |
| 179 | |
| 180 | struct dimminfo { |
| 181 | unsigned int card_type; /* 0x0: unpopulated, |
| 182 | 0xa - 0xf: raw card type A - F */ |
| 183 | u8 type; |
| 184 | enum chip_width width; |
| 185 | enum chip_cap chip_capacity; |
| 186 | unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ |
| 187 | unsigned int sides; |
| 188 | unsigned int banks; |
| 189 | unsigned int ranks; |
| 190 | unsigned int rows; |
| 191 | unsigned int cols; |
| 192 | unsigned int cas_latencies; |
| 193 | unsigned int tAAmin; |
| 194 | unsigned int tCKmin; |
| 195 | unsigned int tWR; |
| 196 | unsigned int tRP; |
| 197 | unsigned int tRCD; |
| 198 | unsigned int tRAS; |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 199 | unsigned int rank_capacity_mb; /* per rank in Megabytes */ |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 200 | u8 spd_data[256]; |
| 201 | }; |
| 202 | |
| 203 | struct pllparam { |
| 204 | u8 kcoarse[2][72]; |
| 205 | u8 pi[2][72]; |
| 206 | u8 dben[2][72]; |
| 207 | u8 dbsel[2][72]; |
| 208 | u8 clkdelay[2][72]; |
| 209 | }; |
| 210 | |
| 211 | struct sysinfo { |
| 212 | u8 maxpi; |
| 213 | u8 pioffset; |
| 214 | u8 pi[8]; |
| 215 | u16 coarsectrl; |
| 216 | u16 coarsedelay; |
| 217 | u16 mediumphase; |
| 218 | u16 readptrdelay; |
| 219 | |
| 220 | int txt_enabled; |
| 221 | int cores; |
| 222 | int boot_path; |
| 223 | int max_ddr2_mhz; |
| 224 | int max_ddr3_mt; |
| 225 | int max_fsb_mhz; |
| 226 | int max_render_mhz; |
| 227 | int enable_igd; |
| 228 | int enable_peg; |
| 229 | u16 ggc; |
| 230 | |
| 231 | int dimm_config[2]; |
| 232 | int dimms_per_ch; |
| 233 | int spd_type; |
| 234 | int channel_capacity[2]; |
| 235 | struct timings selected_timings; |
| 236 | struct dimminfo dimms[4]; |
| 237 | u8 spd_map[4]; |
| 238 | |
| 239 | u8 nodll; |
| 240 | u8 async; |
| 241 | u8 dt0mode; |
| 242 | u8 mvco4x; /* 0 (8x) or 1 (4x) */ |
| 243 | }; |
| 244 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 245 | void pineview_early_init(void); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 246 | u32 decode_igd_memory_size(const u32 gms); |
| 247 | u32 decode_igd_gtt_size(const u32 gsm); |
| 248 | u8 decode_pciebar(u32 *const base, u32 *const len); |
| 249 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 250 | /* Mainboard romstage callback functions */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 251 | void get_mb_spd_addrmap(u8 *spd_addr_map); |
| 252 | void mb_pirq_setup(void); /* optional */ |
| 253 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 254 | struct acpi_rsdp; |
| 255 | unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); |
| 256 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 257 | #endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */ |