| Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 DMP Electronics Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef SOUTHBRIDGE_H |
| 21 | #define SOUTHBRIDGE_H |
| 22 | |
| 23 | #define SB PCI_DEV(0, 7, 0) |
| 24 | #define SB_REG_LPCCR 0x41 |
| 25 | #define SB_REG_FRCSCR 0x42 |
| 26 | #define SB_REG_PIRQ_X_ROUT 0x58 |
| 27 | #define SB_REG_UART_CFG_IO_BASE 0x60 |
| 28 | #define SB_REG_GPIO_CFG_IO_BASE 0x62 |
| 29 | #define SB_REG_CS_BASE0 0x90 |
| 30 | #define SB_REG_CS_BASE_MASK0 0x94 |
| 31 | #define SB_REG_CS_BASE1 0x98 |
| 32 | #define SB_REG_CS_BASE_MASK1 0x9c |
| 33 | #define SB_REG_IPPCR 0xb0 |
| 34 | #define SB_REG_PIRQ_X_ROUT2 0xb4 |
| 35 | #define SB_REG_OCDCR 0xbc |
| 36 | #define SB_REG_IPFCR 0xc0 |
| 37 | #define SB_REG_FRWPR 0xc4 |
| 38 | #define SB_REG_STRAP 0xce |
| 39 | |
| 40 | #define SYSTEM_CTL_PORT 0x92 |
| 41 | |
| 42 | #endif /* SOUTHBRIDGE_H */ |