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Karthikeyan Ramasubramaniana84d4f232022-02-02 10:10:03 -07001/* SPDX-License-Identifier: GPL-2.0-or-later */
2
Felix Held00792002024-01-26 14:41:14 +01003#include <amdblocks/acpi.h>
Jon Murphy3f625072022-04-18 13:19:23 -06004#include <amdblocks/acpimmio.h>
Jon Murphy4f4f32b2022-02-17 20:33:49 -07005#include <amdblocks/amd_pci_util.h>
Mark Hasemeyer7d8f7fb2022-11-18 20:25:44 -07006#include <amdblocks/psp.h>
Robert Zieba6f8f4822022-10-04 12:06:38 -06007#include <amdblocks/xhci.h>
Jon Murphy90424272022-02-16 06:34:39 -07008#include <baseboard/variants.h>
Jon Murphy9e005712022-02-17 14:48:55 -07009#include <console/console.h>
Robert Zieba6f8f4822022-10-04 12:06:38 -060010#include <cpu/x86/smm.h>
Karthikeyan Ramasubramaniana84d4f232022-02-02 10:10:03 -070011#include <device/device.h>
Mark Hasemeyer7d8f7fb2022-11-18 20:25:44 -070012#include <drivers/i2c/tpm/chip.h>
Jon Murphycbf0f982022-02-16 06:47:46 -070013#include <variant/ec.h>
Karthikeyan Ramasubramaniana84d4f232022-02-02 10:10:03 -070014
Felix Heldcf92ecf2022-10-26 00:59:13 +020015/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
16 accessed via I/O ports 0xc00/0xc01. */
Jon Murphy4f4f32b2022-02-17 20:33:49 -070017
18/*
19 * This controls the device -> IRQ routing.
20 *
21 * Hardcoded IRQs:
22 * 0: timer < soc/amd/common/acpi/lpc.asl
23 * 1: i8042 - Keyboard
24 * 2: cascade
25 * 8: rtc0 <- soc/amd/common/acpi/lpc.asl
26 * 9: acpi <- soc/amd/common/acpi/lpc.asl
27 */
28
Felix Held067f7032022-10-25 23:30:43 +020029static const struct fch_irq_routing fch_irq_map[] = {
Jon Murphy4f4f32b2022-02-17 20:33:49 -070030 { PIRQ_A, 12, PIRQ_NC },
31 { PIRQ_B, 14, PIRQ_NC },
32 { PIRQ_C, 15, PIRQ_NC },
33 { PIRQ_D, 12, PIRQ_NC },
34 { PIRQ_E, 14, PIRQ_NC },
35 { PIRQ_F, 15, PIRQ_NC },
36 { PIRQ_G, 12, PIRQ_NC },
37 { PIRQ_H, 14, PIRQ_NC },
38
39 { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
40 { PIRQ_SD, PIRQ_NC, PIRQ_NC },
41 { PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
Jon Murphy4f4f32b2022-02-17 20:33:49 -070042 { PIRQ_GPIO, 11, 11 },
43 { PIRQ_I2C0, 10, 10 },
44 { PIRQ_I2C1, 7, 7 },
45 { PIRQ_I2C2, 6, 6 },
46 { PIRQ_I2C3, 5, 5 },
47 { PIRQ_UART0, 4, 4 },
48 { PIRQ_UART1, 3, 3 },
49
50 /* The MISC registers are not interrupt numbers */
51 { PIRQ_MISC, 0xfa, 0x00 },
52 { PIRQ_MISC0, 0x91, 0x00 },
53 { PIRQ_HPET_L, 0x00, 0x00 },
54 { PIRQ_HPET_H, 0x00, 0x00 },
55};
56
Felix Heldcf92ecf2022-10-26 00:59:13 +020057const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
Felix Helddf14a022022-10-25 23:42:15 +020058{
59 *length = ARRAY_SIZE(fch_irq_map);
60 return fch_irq_map;
61}
62
Jon Murphy90424272022-02-16 06:34:39 -070063static void mainboard_configure_gpios(void)
64{
65 size_t base_num_gpios, override_num_gpios;
66 const struct soc_amd_gpio *base_gpios, *override_gpios;
67
Matt DeVillier4236e2a2022-09-23 13:33:00 -050068 baseboard_gpio_table(&base_gpios, &base_num_gpios);
Jon Murphy90424272022-02-16 06:34:39 -070069 variant_override_gpio_table(&override_gpios, &override_num_gpios);
70
71 gpio_configure_pads_with_override(base_gpios, base_num_gpios,
72 override_gpios, override_num_gpios);
73}
74
Mark Hasemeyer7d8f7fb2022-11-18 20:25:44 -070075static void configure_psp_tpm_gpio(void)
76{
77 const struct device *ti50_dev = DEV_PTR(ti50);
78 struct drivers_i2c_tpm_config *cfg = config_of(ti50_dev);
79
80 psp_set_tpm_irq_gpio(cfg->irq_gpio.pins[0]);
81}
82
Karthikeyan Ramasubramaniana84d4f232022-02-02 10:10:03 -070083static void mainboard_init(void *chip_info)
84{
Jon Murphy90424272022-02-16 06:34:39 -070085 mainboard_configure_gpios();
Jon Murphycbf0f982022-02-16 06:47:46 -070086 mainboard_ec_init();
Mark Hasemeyer7d8f7fb2022-11-18 20:25:44 -070087 configure_psp_tpm_gpio();
Karthikeyan Ramasubramaniana84d4f232022-02-02 10:10:03 -070088}
89
90static void mainboard_enable(struct device *dev)
91{
Jon Murphy3f625072022-04-18 13:19:23 -060092 /* TODO: b/184678786 - Move into espi_config */
93 /* Unmask eSPI IRQ 1 (Keyboard) */
94 pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
Karthikeyan Ramasubramaniana84d4f232022-02-02 10:10:03 -070095}
96
Robert Zieba6f8f4822022-10-04 12:06:38 -060097void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
98{
99 soc_xhci_store_resources(slots, size);
100}
101
Karthikeyan Ramasubramaniana84d4f232022-02-02 10:10:03 -0700102struct chip_operations mainboard_ops = {
103 .init = mainboard_init,
104 .enable_dev = mainboard_enable,
105};